Drive circuit for el display panel

ABSTRACT

To provide a source driver circuit for an EL display panel with reduced variations in output current.  
     A source driver circuit contains unit transistors  634  each of which constitutes a single unit. The 0th bit consists of one unit transistor  634,  the 1st bit consists of two unit transistors  634,  the 2nd bit consists of four unit transistors  634,  the 3rd bit consists of eight unit transistors  634,  the 4th bit consists of 16 unit transistors  634,  and the 5th bit consists of 32 unit transistors  634.    
     Each unit transistor  634  composes a current mirror circuit in conjunction with a transistor  633   a.  Regulating the current Ib flowing through the transistor  633   a  allows for changing the current flowing through the unit transistors  634.  Accurate source driver IC with small variations can be provided by configuring output current circuits with unit transistors and regulating reference currents so that the output current of the unit transistors can be regulated.

TECHNICAL FIELD

The present invention relates to a self-luminous display panel such asan EL display panel which employs organic or inorganicelectroluminescent (EL) elements as well as to a drive circuit (IC) forthe display panel. Also, it relates to an information display apparatusand the like which employ the EL display panel, a drive method for theEL display panel, and the drive circuit for the EL display panel.

BACKGROUND ART

Generally, active-matrix display apparatus display images by arranging alarge number of pixels in a matrix and controlling the light intensityof each pixel according to a video signal. For example, if liquidcrystals are used as an electrochemical substance, the transmittance ofeach pixel changes according to a voltage written into the pixel. Withactive-matrix display apparatus which employ an organicelectroluminescent (EL) material as an electrochemical substance,emission brightness changes according to current written into pixels.

In a liquid crystal display panel, each pixel works as a shutter, andimages are displayed as a backlight is blocked off and revealed by thepixels or shutters. An organic EL display panel is of a self-luminoustype in which each pixel has a light-emitting element. Consequently,organic EL display panels have the advantages of being more viewablethan liquid crystal display panels, requiring no backlighting, havinghigh response speed, etc.

Brightness of each light-emitting element (pixel) in an organic ELdisplay panel is controlled by an amount of current. That is, organic ELdisplay panels differ greatly from liquid crystal display panels in thatlight-emitting elements are driven or controlled by current.

A construction of organic EL display panels can be either asimple-matrix type or active-matrix type. It is difficult to implement alarge high-resolution display panel of the former type although theformer type is simple in structure and inexpensive. The latter typeallows a large high-resolution display panel to be implemented, butinvolves a problem that it is a technically difficult control method andis relatively expensive. Currently, active-matrix type display panelsare developed intensively. In the active-matrix type display panel,current flowing through the light-emitting elements provided in eachpixel is controlled by thin-film transistors (transistors) installed inthe pixels.

Such an organic EL display panel of an active-matrix type is disclosedin Japanese Patent Laid-Open No. 8-234683. An equivalent circuit for onepixel of the display panel is shown in FIG. 62. A pixel 16 consists ofan EL element 15 which is a light-emitting element, a first transistor11 a, a second transistor 11 b, and a storage capacitance 19. The ELelement 15 is an organic electroluminescent (EL) element. According tothe present specification, the transistor 11 a which supplies (controls)current to the EL element 15 is referred to as a driver transistor 11. Atransistor, such as the transistor 11 b shown in FIG. 62, which operatesas a switch is referred to as a switching transistor 11.

The organic EL element 15, in many cases, may be referred to as an OLED(organic light-emitting diode) because of its rectification. In FIG. 62or the like, a diode symbol is used for the EL element 15.

Incidentally, the EL element 15 according to the present specificationis not limited to an OLED. It may be of any type as long as itsbrightness is controlled by the amount of current flowing through theelement 15. Examples include an inorganic EL element, a whitelight-emitting diode consisting of a semiconductor, atypicallight-emitting diode, and a light-emitting transistor. Rectification isnot necessarily required of the EL element 15. Bidirectional diodes arealso available. The EL element 15 according to the present specificationmay be any of the above elements.

In the example of FIG. 62, a source terminal (S) of the P-channeltransistor 11 a is designated as Vdd (power supply potential) and acathode of the EL element 15 is connected to ground potential (Vk). Onthe other hand, an anode is connected to a drain terminal (D) of thetransistor 11 b. Besides, a gate terminal of the P-channel transistor 11a is connected to a gate signal line 17 a, a source terminal isconnected to a source signal line 18, and a drain terminal is connectedto the storage capacitance 19 and a gate terminal (G) of the P-channeltransistor 11 a.

To drive the pixel 16, a video signal which represents brightnessinformation is first applied to the source signal line 18 with the gatesignal line 17 a selected. Then, the transistor 11 a conducts, thestorage capacitance 19 is charged or discharged, and gate potential ofthe transistor 11 b matches the potential of the video signal. When thegate signal line 17 a is deselected, the transistor 11 a is turned offand the transistor 11 b is cut off electrically from the source signalline 18. However, the gate potential of the transistor 11 a ismaintained stably by the storage capacitance (capacitor) 19. Currentdelivered to the EL element 15 via the transistor 11 a depends ongate-source voltage Vgs of the transistor 11 a and the EL element 15continues to emit light at an intensity which corresponds to the amountof current supplied via the transistor 11 a.

Since liquid crystal display panels are not self-luminous devices, thereis a problem that they cannot display images without backlighting. Also,there has been a problem that a certain thickness is required to providea backlight, which makes the display panel thicker. Besides, to displaycolors on a liquid crystal display panel, color filters must be used.Therefore, there has been a problem of the lowered usability of light.Also, there has been the problem of narrow color reproduction range.

Organic EL display panels are made of low-temperature polysilicontransistor arrays. However, since organic EL elements use current toemit light, there has been a problem that variations in thecharacteristics of the transistors will cause display irregularities.

The display irregularities can be reduced using current programming ofpixels. For current programming, a current-driven driver circuit isrequired. However, with a current-driven driver circuit, variations willalso occur in transistor elements which compose a current output stage.This in turn causes variations in gradation output currents from outputterminals, making it impossible to display images properly.

DISCLOSURE OF THE INVENTION

To achieve this object, a driver circuit for an EL display panel (ELdisplay apparatus) according to the present invention comprises aplurality of transistors which output unit currents and produces anoutput current by varying the number of transistors. Also, the drivercircuit is characterized by comprising a multi-stage current mirrorcircuit. A transistor group which delivers signals via voltages isformed densely. Also, signals are delivered between the transistor groupand current mirror circuit group via currents. Besides, referencecurrents are produced by a plurality of transistors.

A first invention of the present invention is a driver circuit for an ELdisplay panel comprising:

-   -   reference current generating means of generating a reference        current;    -   a first current source which is fed the reference current from        the reference current generating means and outputs a first        current which corresponds to the reference current to a        plurality of second current sources;    -   the second current sources which are fed the first current        outputted from the first current source and output a second        current which corresponds to the first current to a plurality of        third current sources; and    -   the third current sources which are fed the second current        outputted from the second current sources and output a third        current which corresponds to the second current to a plurality        of fourth current sources,    -   characterize in that among the fourth current sources, an        appropriate number of unit current sources are selected        according to input image data.

A second invention of the present invention is a driver circuit for anEL display panel comprising:

-   -   a plurality of current generator circuits each of which has unit        transistors equal in number to a power of two;    -   switch circuits connected to the respective current generator        circuits;    -   internal wiring connected to output terminals; and    -   a control circuit which turns on and off the switch circuits        according to input data,    -   wherein one end of each switch circuit is connected to the        current generator circuit and the other end is connected to the        internal wiring.

A third invention of the present invention is the driver circuit for anEL display panel according to the second invention of the presentinvention, wherein:

-   -   channel width W of the unit transistors is from 2 to 9 μm both        inclusive, and    -   size (WL) of the transistors is 4 square μm or more.

A fourth invention of the present invention is the driver circuit for anEL display panel according to the second invention of the presentinvention, wherein:

-   -   a ratio of channel length L to the channel width W of the unit        transistors is two or larger; and

power supply voltage used is between 2.5 V and 9 V both inclusive.

A fifth invention of the present invention is a driver circuit for an ELdisplay panel comprising:

-   -   a first output current circuit consisting of a plurality of unit        transistors which pass a first unit current;    -   a second output current circuit consisting of a plurality of        unit transistors which pass a second unit current; and    -   an output stage which produces an output by adding an output        current of the first output current circuit and an output        current of the second output current circuit,    -   wherein the first unit current is smaller than the second unit        current,    -   the first output current circuit operates in a low gradation        region and a high gradation region according to gradations, and    -   the second output current circuit operates in the high gradation        region according to gradations, and output current values of the        first output current circuit do not change in the high gradation        region when the second output current circuit operates.

A sixth invention of the present invention is a driver circuit for an ELdisplay panel comprising:

-   -   a programming current generator circuit which has a plurality of        unit transistors corresponding to output terminals;    -   first transistors which generate a first reference current which        defines a current flowing through the unit transistors;    -   gate wiring connected to gate terminals of the plurality of        first transistors; and    -   a second and third transistors whose gate terminals are        connected to the gate wiring and which form current mirror        circuits in conjunction with the first transistors,    -   wherein a second reference current is supplied to the second and        third transistors.

A seventh invention of the present invention is the driver circuit foran EL display panel according to the sixth invention of the presentinvention, comprising:

-   -   a programming current generator circuit which has a plurality of        unit transistors corresponding to output terminals;    -   a plurality of first transistors which form current mirror        circuits in conjunction with the unit transistors; and    -   a second transistor which generates a reference current flowing        through the first transistors,    -   wherein the reference current generated by the second transistor        branches through the plurality of first transistors.

An eighth invention of the present invention is the driver circuit foran EL display panel according to the sixth or seventh invention of thepresent invention, wherein in a driver IC chip which includes the drivercircuit, the third transistor is electrically connected, in an area inwhich the first reference current supply wirings are placed, to twooutermost placed wirings of the reference current supply wiring groupplaced in the area.

A ninth invention of the present invention is an EL display apparatuscomprising:

-   -   a first substrate on which driver transistors are placed in a        matrix and which contains a display area consisting of EL        elements formed corresponding to the driver transistors;    -   a source driver IC which applies a programming current or        voltage to the driver transistors;    -   a first wiring formed on the first substrate located under the        source driver IC;    -   a second wiring electrically connected to the first wiring and        formed between the source driver IC and the display area; and    -   anode wiring which branches from the second wiring and applies        an anode voltage to pixels in the display area.

A tenth invention of the present invention is the EL display apparatusaccording to the ninth invention of the present invention, wherein thefirst wiring has a light shielding function.

An eleventh invention of the present invention is an EL displayapparatus comprising:

-   -   a display area where pixels with EL elements are formed in a        matrix;    -   driver transistors which supply light-emitting current to the EL        elements; and    -   a source driver circuit which supplies programming current to        the driver transistors,    -   wherein the driver transistors are P-channel transistors, and    -   transistors which generate the programming current in the source        driver circuit are N-channel transistors.

A twelfth invention of the present invention is an EL display apparatuscomprising:

-   -   a display area where EL elements, driver transistors which        supply light-emitting current to the EL elements, first        switching elements which form paths between the driver        transistors and the EL elements, and second switching elements        which form paths between the driver transistors and source        signal lines are formed in a matrix;    -   a first gate driver circuit which performs on/off control of the        first switching elements;    -   a second gate driver circuit which performs on/off control of        the second switching elements;    -   a source driver circuit which applies video signals to the        transistor elements; and    -   a source driver circuit which supplies programming current to        the driver transistors,    -   wherein the driver transistors are P-channel transistors, and    -   transistors which generate the programming current in the source        driver circuit are N-channel transistors.

A thirteenth invention of the present invention is an EL displayapparatus comprising:

-   -   EL elements;    -   P-channel driver transistors which supply light-emitting current        to the EL elements;    -   switching transistors formed between the EL elements and the        driver transistors;    -   a source driver circuit which supplies programming current;    -   and gate driver circuits which keep the switching transistors        off for two horizontal scanning periods or longer in one frame        period.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a pixel in a display panel according to thepresent invention;

FIG. 2 is a block diagram of a pixel in a display panel according to thepresent invention;

FIG. 3 is an explanatory diagram illustrating operation of a displaypanel according to the present invention;

FIG. 4 is an explanatory diagram illustrating operation of a displaypanel according to the present invention;

FIG. 5 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 6 is a block diagram of a display apparatus according to thepresent invention;

FIG. 7 is an explanatory diagram illustrating a manufacturing method ofa display panel according to the present invention;

FIG. 8 is a block diagram of a display apparatus according to thepresent invention;

FIG. 9 is a block diagram of a display apparatus according to thepresent invention;

FIG. 10 is a sectional view of a display panel according to the presentinvention;

FIG. 11 is a sectional view of a display panel according to the presentinvention;

FIG. 12 is an explanatory diagram illustrating a display panel accordingto the present invention;

FIG. 13 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 14 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 15 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 16 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 17 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 18 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 19 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 20 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 21 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 22 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 23 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 24 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 25 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 26 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 27 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 28 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 29 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 30 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 31 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 32 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 33 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 34 is a block diagram of a display apparatus according to thepresent invention;

FIG. 35 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 36 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 37 is a block diagram of a display apparatus according to thepresent invention;

FIG. 38 is a block diagram of a display apparatus according to thepresent invention;

FIG. 39 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 40 is a block diagram of a display apparatus according to thepresent invention;

FIG. 41 is a block diagram of a display apparatus according to thepresent invention;

FIG. 42 is a block diagram of a pixel in a display panel according tothe present invention;

FIG. 43 is a block diagram of a pixel in a display panel according tothe present invention;

FIG. 44 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 45 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 46 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 47 is a block diagram of a pixel in a display panel according tothe present invention;

FIG. 48 is a block diagram of a display apparatus according to thepresent invention;

FIG. 49 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 50 is a block diagram of a pixel in a display panel according tothe present invention;

FIG. 51 is a diagram of a pixel in a display panel according to thepresent invention;

FIG. 52 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 53 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 54 is a block diagram of a pixel in a display panel according tothe present invention;

FIG. 55 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 56 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 57 is an explanatory diagram illustrating a cell phone according tothe present invention;

FIG. 58 is an explanatory diagram illustrating a viewfinder according tothe present invention;

FIG. 59 is an explanatory diagram illustrating a video camera accordingto the present invention;

FIG. 60 is an explanatory diagram illustrating a digital cameraaccording to the present invention;

FIG. 61 is an explanatory diagram illustrating a TV (monitor) accordingto the present invention;

FIG. 62 is a block diagram of a pixel in a conventional display panel;

FIG. 63 is a functional block diagram of a driver circuit according tothe present invention;

FIG. 64 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 65 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 66 is an explanatory diagram illustrating a voltage-based deliverytype multi-stage current mirror circuit;

FIG. 67 is an explanatory diagram illustrating a current-based deliverytype multi-stage current mirror circuit;

FIG. 68 is an explanatory diagram illustrating a driver circuitaccording to another example of the present invention;

FIG. 69 is an explanatory diagram illustrating a driver circuitaccording to another example of the present invention;

FIG. 70 is an explanatory diagram illustrating a driver circuitaccording to another example of the present invention;

FIG. 71 is an explanatory diagram illustrating a driver circuitaccording to another example of the present invention;

FIG. 72 is an explanatory diagram illustrating a conventional drivercircuit;

FIG. 73 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 74 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 75 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 76 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 77 is an explanatory diagram illustrating a control method of adriver circuit according to the present invention;

FIG. 78 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 79 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 80 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 81 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 82 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 83 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 84 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 85 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 86 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 87 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 88 is an explanatory diagram illustrating a drive method accordingto the present invention;

FIG. 89 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 90 is an explanatory diagram illustrating a drive method accordingto the present invention;

FIG. 91 is a block diagram of an EL display apparatus according to thepresent invention;

FIG. 92 is a block diagram of an EL display apparatus according to thepresent invention;

FIG. 93 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 94 is an explanatory diagram illustrating a driver circuitaccording to the present invention;

FIG. 95 is a block diagram of an EL display apparatus according to thepresent invention;

FIG. 96 is a block diagram of an EL display apparatus according to thepresent invention;

FIG. 97 is a block diagram of an EL display apparatus according to thepresent invention;

FIG. 98 is a block diagram of an EL display apparatus according to thepresent invention;

FIG. 99 is a block diagram of an EL display apparatus according to thepresent invention;

FIG. 100 is a sectional view of an EL display apparatus according to thepresent invention;

FIG. 101 is a sectional view of an EL display apparatus according to thepresent invention;

FIG. 102 is a block diagram of an EL display apparatus according to thepresent invention;

FIG. 103 is a block diagram of an EL display apparatus according to thepresent invention;

FIG. 104 is a block diagram of an EL display apparatus according to thepresent invention;

FIG. 105 is a block diagram of an EL display apparatus according to thepresent invention;

FIG. 106 is a block diagram of an EL display apparatus according to thepresent invention;

FIG. 107 is a block diagram of an EL display apparatus according to thepresent invention;

FIG. 108 is a block diagram of an EL display apparatus according to thepresent invention;

FIG. 109 is a block diagram of an EL display apparatus according to thepresent invention;

FIG. 110 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 111 is a block diagram of a gate driver circuit according to thepresent invention;

FIG. 112 is a timing chart of the gate driver circuit shown in FIG. 111;

FIG. 113 is a block diagram of part of a gate driver circuit accordingto the present invention;

FIG. 114 is a timing chart of the gate driver circuit shown in FIG. 113;

FIG. 115 is an explanatory diagram illustrating a drive method of an ELdisplay apparatus according to the present invention;

FIG. 116 is an explanatory diagram illustrating a drive method of an ELdisplay apparatus according to the present invention;

FIG. 117 is an explanatory diagram illustrating a drive circuit of an ELdisplay apparatus according to the present invention;

FIG. 118 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 119 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 120 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 121 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 122 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 123 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 124 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 125 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 126 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 127 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 128 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 129 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 130 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 131 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 132 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 133 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 134 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 135 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 136 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 137 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 138 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 139 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 140 is an explanatory diagram illustrating a display panelaccording to the present invention;

FIG. 141 is an explanatory diagram illustrating a display panelaccording to the present invention;

FIG. 142 is an explanatory diagram illustrating a display panelaccording to the present invention;

FIG. 143 is an explanatory diagram illustrating a display panelaccording to the present invention;

FIG. 144 is a block diagram of a pixel in a display panel according tothe present invention;

FIG. 145 is a block diagram of a pixel in a display panel according tothe present invention;

FIG. 146 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 147 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 148 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 149 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 150 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 151 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 152 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 153 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 154 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 155 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 156 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 157 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 158 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 159 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 160 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 161 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 162 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 163 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 164 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 165 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 166 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 167 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 168 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 169 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 170 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 171 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 172 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 173 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 174 is an explanatory diagram illustrating a drive method of an ELdisplay apparatus according to the present invention;

FIG. 175 is an explanatory diagram illustrating a drive method of an ELdisplay apparatus according to the present invention;

FIG. 176 is an explanatory diagram illustrating a drive circuit of an ELdisplay apparatus according to the present invention;

FIG. 177 is an explanatory diagram illustrating a drive circuit of an ELdisplay apparatus according to the present invention;

FIG. 178 is an explanatory diagram illustrating a drive circuit of an ELdisplay apparatus according to the present invention;

FIG. 179 is an explanatory diagram illustrating a drive circuit of an ELdisplay apparatus according to the present invention;

FIG. 180 is an explanatory diagram illustrating a drive circuit of an ELdisplay apparatus according to the present invention;

FIG. 181 is an explanatory diagram illustrating a drive circuit of an ELdisplay apparatus according to the present invention;

FIG. 182 is an explanatory diagram illustrating an EL display apparatusaccording to the present invention;

FIG. 183 is an explanatory diagram illustrating an EL display apparatusaccording to the present invention;

FIG. 184 is an explanatory diagram illustrating an EL display apparatusaccording to the present invention;

FIG. 185 is an explanatory diagram illustrating an EL display apparatusaccording to the present invention;

FIG. 186 is an explanatory diagram illustrating a drive method of an ELdisplay apparatus according to the present invention;

FIG. 187 is an explanatory diagram illustrating a drive method of an ELdisplay apparatus according to the present invention;

FIG. 188 is an explanatory diagram illustrating a drive circuit of an ELdisplay apparatus according to the present invention;

FIG. 189 is an explanatory diagram illustrating a drive circuit of an ELdisplay apparatus according to the present invention;

FIG. 190 is an explanatory diagram illustrating a drive circuit of an ELdisplay apparatus according to the present invention;

FIG. 191 is an explanatory diagram illustrating a drive circuit of an ELdisplay apparatus according to the present invention;

FIG. 192 is an explanatory diagram illustrating a drive method of an ELdisplay apparatus according to the present invention;

FIG. 193 is an explanatory diagram illustrating a drive method of an ELdisplay apparatus according to the present invention;

FIG. 194 is an explanatory diagram illustrating a drive method of an ELdisplay apparatus according to the present invention;

FIG. 195 is an explanatory diagram illustrating a drive method of an ELdisplay apparatus according to the present invention;

FIG. 196 is an explanatory diagram illustrating a drive circuit of an ELdisplay apparatus according to the present invention;

FIG. 197 is an explanatory diagram illustrating a drive method of an ELdisplay apparatus according to the present invention;

FIG. 198 is an explanatory diagram illustrating a drive method of an ELdisplay apparatus according to the present invention;

FIG. 199 is an explanatory diagram illustrating a drive circuit of an ELdisplay apparatus according to the present invention;

FIG. 200 is an explanatory diagram illustrating a drive method of an ELdisplay apparatus according to the present invention;

FIG. 201 is an explanatory diagram illustrating an EL display apparatusaccording to the present invention;

FIG. 202 is an explanatory diagram illustrating an EL display apparatusaccording to the present invention;

FIG. 203 is an explanatory diagram illustrating an EL display apparatusaccording to the present invention;

FIG. 204 is an explanatory diagram illustrating an EL display apparatusaccording to the present invention;

FIG. 205 is an explanatory diagram illustrating an EL display apparatusaccording to the present invention;

FIG. 206 is an explanatory diagram illustrating an EL display apparatusaccording to the present invention;

FIG. 207 is an explanatory diagram illustrating an EL display apparatusaccording to the present invention;

FIG. 208 is an explanatory diagram illustrating an EL display apparatusaccording to the present invention;

FIG. 209 is an explanatory diagram illustrating an EL display apparatusaccording to the present invention;

FIG. 210 is an explanatory diagram illustrating an EL display apparatusaccording to the present invention;

FIG. 211 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 212 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 213 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 214 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 215 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 216 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 217 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 218 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 219 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 220 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 221 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 222 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 223 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 224 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 225 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 226 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 227 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 228 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

DESCRIPTION OF SYMBOLS

-   11 Transistor (thin-film transistor)-   12 Gate driver IC (circuit)-   14 Source driver IC (circuit)-   15 EL (element) (light-emitting element)-   16 Pixel-   17 Gate signal line-   18 Source signal line-   19 Storage capacitance (additional capacitor, additional    capacitance)-   50 Display screen-   51 Write pixel (row)-   52 Non-display pixel (non-display area, non-illuminated area)-   53 Display pixel (display area, illuminated area)-   61 Shift register-   62 Inverter-   63 Output buffer-   71 Array board (display panel)-   72 Laser irradiation range (laser spot)-   73 Positioning marker-   74 Glass substrate (array board)-   81 Control IC (circuit)-   82 Power supply IC (circuit)-   83 Printed board-   84 Flexible board-   85 Sealing lid-   86 Cathode wiring-   87 Anode wiring (Vdd)-   88 Data signal line-   89 Gate control signal line-   101 Bank (rib)-   102 Interlayer insulating film-   104 Contact connector-   105 Pixel electrode-   106 Cathode electrode-   107 Desiccant-   108 λ/4 plate-   109 Polarizing plate-   111 Thin encapsulation film-   281 Dummy pixel (row)-   341 Output stage circuit-   371 OR circuit-   401 Illumination control line-   471 Reverse bias line-   472 Gate potential control line-   561 Electronic regulator circuit-   562 SD (source-drain) short circuit of a transistor-   571 Antenna-   572 Key-   573 Housing-   574 Display panel-   581 Eye ring-   582 Magnifying lens-   583 Convex lens-   591 Supporting point (pivot point)-   592 Taking lens-   593 Storage section-   594 Switch-   601 Body-   602 Photographic section-   603 Shutter switch-   611 Mounting frame-   612 Leg-   613 Mount-   614 Fixed part-   631 Current source-   632 Current source-   633 Current source-   641 Switch (on/off means)-   634 Current source (single unit)-   643 Internal wiring-   651 Regulator (current regulating means)-   681 Transistor group-   691 Resistor (current limiting means, predetermined-current    generating means)-   692 Decoder circuit-   693 Level shifter circuit-   701 Counter (counting means)-   702 NOR-   703 AND-   704 Current output circuit-   711 Padder circuit-   721 D/A converter-   722 Operational amplifier-   731 Analog switch (on/off means)-   732 Inverter-   761 Output pad (output signal terminal)-   771 Reference current source-   772 Current control circuit-   781 Temperature detection circuit-   782 Temperature control circuit-   931 Cascade current connection line-   932 Reference current signal line-   941 i Current input terminal-   941 o Current output terminal-   951 Base anode line (anode voltage line)-   952 Anode wiring-   953 Connection terminal-   961 Connection anode line-   962 Common anode line-   971 Contact hole-   991 Base cathode line-   992 Input signal line-   1001 Connection resin (conductive resin, anisotropic conductive    resin)-   1011 Light absorbing film-   1012 Resin bead-   1013 Sealing resin-   1021 Circuit forming section-   1051 Gate voltage line-   1091 Power supply circuit (IC)-   1092 Power supply IC control signal-   1093 Gate driver circuit control signal-   1111 Unit gate output circuit-   1241 Adjusting transistor-   1251 Cutting site-   1252 Common terminal-   1341 Dummy transistor-   1351 Transistor (single-unit transistor)-   1352 Sub-transistor-   1401 Switching circuit (analog switch)-   1491 Flash memory (setting storage means)-   1501 Laser device-   1502 Laser light-   1503 Resistor array (adjustment resistor)-   1521 Switch (on/off means)-   1531 Steady-state transistor-   1541 NAND circuit-   1601 Capacitor-   1611 Sleep switch (on/off control means, reference current on/off    means)-   1671 Protective diode-   1731 Coincidence circuit (gradation detection circuit)-   1741 Output switching circuit-   1742 Changeover switch-   1821 Anode connection circuit-   2011 Coil (transformer)-   2012 Control circuit-   2013 Diode-   2014 Capacitor-   2021 Switch-   2022 Temperature sensor-   2041 Level shifter circuit-   2042 Gate driver control signal-   2061 Bonding layer (connection layer, heat conduction layer, and    adhesion layer)-   2062 Chassis (Metal chassis)-   2063 Projections and depressions-   2071 Hole-   2211 Control electrode-   2212 Video signal circuit-   2213 Electron emission protuberance-   2214 Holding circuit-   2215 On/off control circuit-   2221 Selection signal line-   2222 On/off signal line-   2281 Sealing resin

BEST MODE FOR CARRYING OUT THE INVENTION

Some parts of drawings herein are omitted and/or enlarged/reduced hereinfor ease of understanding and/or illustration. For example, in asectional view of a display panel shown in FIG. 11, a thin encapsulationfilm 111 and the like are shown as being fairly thick. On the otherhand, in FIG. 10, a sealing lid 85 is shown as being thin. Some partsare omitted. For example, although the display panel according to thepresent invention requires a phase film such as a circular polarizingplate to prevent reflection, the phase film is omitted in drawingsherein. This also applies to the drawings below. Besides, the same orsimilar forms, materials, functions, or operations are denoted by thesame reference numbers or characters.

Incidentally, what is described with reference to drawings or the likecan be combined with other examples or the like even if not notedspecifically. For example, a touch panel or the like can be attached toa display panel in FIG. 8 to provide an information display apparatusshown in FIGS. 19 and 59 to 61. Also, a magnifying lens 1582 can bemounted to configure a view finder (see FIG. 58) used for a video camera(see FIG. 159, etc.) or the like. Also, drive methods described withreference to FIG. 4, 15, 18, 21, 23, etc. can be applied to any displayapparatus or display panel according to the present invention.

Also, thin-film transistors are cited herein as driver transistors 11and switching transistors 11, this is not restrictive. Thin-film diodes(TFDs) or ring diodes may be used instead. Also, the present inventionis not limited to thin-film elements, and transistors formed on siliconwafers may also be used. In this case, a board 71 can be made of asilicon wafer. Needless to say, FETs, MOS-FETs, MOS transistors, orbipolar transistors may also be used. They are basically, thin-filmtransistors. It goes without saying that the present invention may alsouse varistors, thyristors, ring diodes, photodiodes, phototransistors,or PLZT elements. That is, the transistor 11, gate driver circuit 12,and source driver circuit 14 according to the present invention can useany of the above elements.

An EL panel according to the present invention will be described belowwith reference to drawings. As shown in FIG. 10, an organic EL displaypanel consists of a glass substrate (array board) 71, transparentelectrodes 105 formed as pixel electrodes, at least one organicfunctional layer (EL layer) 15, and a metal electrode (reflective film)(cathode) 106, which are stacked one on top of another, where theorganic functional layer consists of an electron transport layer,light-emitting layer, positive hole transport layer, etc. The organicfunctional layer (EL layer) 15 emits light when a positive voltage isapplied to the anode or transparent electrodes (pixel electrodes) 105and a negative voltage is applied to the cathode or metal electrode(reflective electrode) 106, i.e., when a direct current is appliedbetween the transparent electrodes 105 and metal electrode 106.

Preferably, the metal electrode 106 is made of metal with a small workfunction, such as lithium, silver, aluminum, magnesium, indium, copper,or an alloy thereof. In particular, it is preferable to use, forexample, an Al—Li alloy. The transparent electrodes 105 may be made of,conductive materials with a large work function such as ITO, or gold andthe like. If gold is used as an electrode material, the electrodesbecome translucent. Incidentally, IZO or other material may be usedinstead of ITO. This also applies to other pixel electrodes 105.

Incidentally, a desiccant 107 is placed in a space between the sealinglid 85 and array board 71. This is because the organic EL film 15 isvulnerable to moisture. The desiccant 107 absorbs water penetrating asealant and thereby prevents deterioration of the organic EL film 15.

Although the sealing lid 85 is used for sealing in FIG. 10, the film 111(this may be a thin film, i.e., a thin encapsulation film) may be usedfor sealing as shown in FIG. 11. The encapsulation film (thinencapsulation film) 111 may be, for example, an electrolytic capacitorfilm on which DLC (diamond-like carbon) is vapor-deposited. This filmfeatures extremely low moisture penetration (high moisture resistance)It is used as the thin encapsulation film 111. Also, it goes withoutsaying that DLC diamond-like carbon) film may be vapor-depositeddirectly on a surface of the metal electrode 106. Besides, the thinencapsulation film may be formed by laminating thin resin films andmetal films.

Desirably, film thickness of the thin film is such that n·d is equal toor less than main emission wavelength λ of the EL element 15 (where n isthe refraction factor of the thin film, or the sum of refraction factorsif two or more thin films are laminated (n·d of each thin film iscalculated); d is the film thickness of the thin film, or the sum ofrefraction factors if two or more thin films are laminated). Bysatisfying this condition, it is possible to more than double theefficiency of light extraction from the EL element 15 compared to when aglass substrate is used for sealing. Also, an alloy, mixture, orlaminate of aluminum and silver may be used.

A technique which uses a thin encapsulation film 111 for sealing insteadof a sealing lid 85 as described above is called thin filmencapsulation. In the case of “underside extraction (see FIG. 10; lightis extracted in the direction of the arrow in FIG. 10)” in which lightis extracted from the side of the board 71, thin film encapsulationinvolves forming an EL film and then forming an aluminum electrode whichwill serve as a cathode on the EL film. Then, a resin layer is formed asa cushioning layer on the aluminum layer. An organic material such asacrylic or epoxy may be used for a cushioning layer. Suitable filmthickness is from 1 μm to 10 μm (both inclusive). More preferably, thefilm thickness is from 2 μm to 6 μm (both inclusive). The encapsulationfilm 74 is formed on the cushioning film. Without the cushioning film,structure of the EL film would be deformed by stress, resulting instreaky defects. As described above, the thin encapsulation film 111 maybe made, for example, of DLC (diamond-like carbon) or an electrolyticcapacitor of a laminar structure (structure consisting of thindielectric films and aluminum films vapor-deposited alternately).

In the case of “topside extraction (see FIG. 11; light is extracted inthe direction of the arrow in FIG. 11)” in which light is extracted fromthe side of the EL layer 15, thin film encapsulation involves formingthe EL film 15 and then forming an Ag—Mg film 20 angstrom (inclusive) to300 angstrom thick on the EL film 15 to serve as a cathode (anode). Atransparent electrode such as ITO is formed on the film to reduceresistance. Then, a resin layer is formed as a cushioning layer on theelectrode film. A thin encapsulation film 111 is formed on thecushioning film.

Half the light produced by the organic EL layer 15 is reflected by themetal electrode 106 and emitted through the array board 71. However, themetal electrode 106 reflects extraneous light, resulting in glare, whichlowers display contrast. To deal with this situation, a λ/4 phase plate108 and polarizing plate (polarizing film) 109 are placed on the arrayboard 71. These are generally called circular polarizing plates(circular polarizing sheets).

Incidentally, if the pixels are reflective electrodes, the lightproduced by the organic EL layer 15 is emitted upward. Thus, needless tosay, the phase plate 108 and polarizing plate 109 are placed on the sidefrom which light is emitted. Reflective pixels can be obtained by makingpixel electrodes 105 from aluminum, chromium, silver, or the like. Also,by providing projections (or projections and depressions) on a surfaceof the pixel electrodes 105, it is possible to increase an interfacewith the organic EL layer 15, and thereby increase the light-emittingarea, resulting in improved light-emission efficiency. Incidentally, thereflective film which serves as the cathode 106 (anode 105) is made as atransparent electrode. If reflectance can be reduced to 30% or less, nocircular polarizing plate is required. This is because glare is reducedgreatly. Light interference is reduced as well.

Preferably, LDD (low doped drain) structure is used for the transistors11. The EL elements will be described herein taking organic EL elements(known by various abbreviations including OEL, PEL, PLED, OLED) 15 as anexample, but this is not restrictive and inorganic EL elements may beused as well.

An organic EL display panel of active-matrix type must satisfy twoconditions: that it is capable of selecting a specific pixel and givenecessary display information and that it is capable of passing currentthrough the EL element throughout one frame period.

To satisfy the two conditions, in a conventional organic EL pixelconfiguration shown in FIG. 62, a switching transistor is used as afirst transistor 11 b to select the pixel and a driver transistor isused as a second transistor 11 a to supply current to an EL element (ELfilm) 15.

To display a gradation using this configuration, a voltage correspondingto the gradation must be applied the gate of the driver transistor 11 a.Consequently, variations in a turn-on current of the driver transistor11 a appear directly in display.

The turn-on current of a transistor is extremely uniform if thetransistor is monocrystalline. However, in the case of a low-temperaturepolycrystalline transistor formed on an inexpensive glass substrate bylow-temperature polysilicon technology at a temperature not higher than450, its threshold varies in a range of ±0.2 V to 0.5 V. The turn-oncurrent flowing through the driver transistor 11 a varies accordingly,causing display irregularities. The irregularities are caused not onlyby variations in the threshold voltage, but also by mobility of thetransistor and thickness of a gate insulating film. Characteristics alsochange due to degradation of the transistor 11.

This phenomenon is not limited to low-temperature polysilicontechnologies, and can occur in transistors formed on semiconductor filmsgrown in solid-phase (CGS) by high-temperature polysilicon technology ata process temperature of 450 degrees (centigrade) or higher. Besides,the phenomenon can occur in organic transistors and amorphous silicontransistors.

As described below, the present invention provides a configuration orscheme which can accommodate the above technologies. Description will begiven herein mainly of transistors produced by the low-temperaturepolysilicon technology.

In a method which displays gradations by the application of voltage asshown in FIG. 62, device characteristics must be controlled strictly toobtain a uniform display. However, current low-temperaturepolycrystalline polysilicon transistors or the like cannot satisfy aspecification which prescribes that variations be kept within apredetermined range.

Each pixel structure in an EL display panel according to the presentinvention comprises at least four transistors 11 and an EL element asshown concretely in FIG. 1. Pixel electrodes are configured to overlapwith a source signal line. Specifically, the pixel electrodes 105 areformed on an insulating film or planarized acrylic film formed on thesource signal line 18 for insulation. A structure in which pixelelectrodes overlap with at least part of the source signal line 18 isknown as a high aperture (HA) structure. This reduces unnecessary lightinterference and allows proper light emission.

When the gate signal line (first scanning line) 17 a is activated (aturn-on voltage is applied), a current to be passed through the ELelement 15 is delivered from the source driver circuit 14 via the drivertransistor 11 a and switching transistor 11 c of the EL element 15.Also, upon activation of (application of a turn-on voltage to) the gatesignal line 17 a, the transistor 11 b opens to cause a short circuitbetween gate and drain of the transistor 11 a and gate voltage (or drainvoltage) of the transistor 11 a is stored in a capacitor (storagecapacitance, additional capacitance) 19 connected between the gate anddrain of the transistor 11 a (see FIG. 3(a)).

Preferably, the capacitor (storage capacitance) 19 should be from 0.2 pFto 2 pF both inclusive. More preferably, the capacitor (storagecapacitance) 19 should be from 0.4 pF to 1.2 pF both inclusive. Thecapacity of the capacitor 19 is determined taking pixel size intoconsideration. If the capacity needed for a single pixel is Cs (pF) andan area (rather than an aperture ratio) occupied by the pixel is Sp(square μm), a condition 500/Sp≦Cs≦20000/Sp, and more preferably acondition 1000/Sp≦Cs≦10000/Sp should be satisfied. Since gate capacityof the transistor is small, Q as referred to here is the capacity of thestorage capacitance (capacitor) 19 alone.

The gate signal line 17 a is deactivated (a turn-off voltage isapplied), a gate signal line 17 b is activated, and a current path isswitched to a path which includes the first transistor 11 a, atransistor 11 d connected to the EL element 15, and the EL element 15 todeliver the stored current to the EL element 15 (see FIG. 3(b)).

In this circuit, a single pixel contains four transistors 11. The gateof the transistor 11 a is connected to the source of the transistor 11b. The gates of the transistors 11 b and 11 c are connected to the gatesignal line 17 a. The drain of the transistor 11 b is connected to thesource of the transistor 11 c and source of the transistor 11 d. Thedrain of the transistor 11 c is connected to the source signal line 18.The gate of the transistor 11 d is connected to the gate signal line 17b and the drain of the transistor 11 d is connected to the anodeelectrode of the EL element 15.

Incidentally, all the transistors in FIG. 1 are P-channel transistors.Compared to N-channel transistors, P-channel transistors have more orless lower mobility, but they are preferable because they are moreresistant to voltage and degradation. However, the EL element accordingto the present invention is not limited to P-channel transistors and thepresent invention may employ N-channel transistors alone. Also, thepresent invention may employ both N-channel and P-channel transistors.

Optimally, P-channel transistors should be used for all the transistors11 composing pixels as well as for the built-in gate drivers 12. Bycomposing an array solely of P-channel transistors, it is possible toreduce the number of masks to 5, resulting in low costs and high yields.

To facilitate understanding of the present invention, the configurationof the EL element according to the present invention will be describedbelow with reference to FIG. 3. The EL element according to the presentinvention is controlled using two timings. The first timing is the onewhen required current values are stored. Turning on the transistor 11 band transistor 11 c with this timing provides an equivalent circuitshown in FIG. 3(a). A predetermined current Iw is applied from signallines. This makes the gate and drain of the transistor 11 a connected,allowing the current Iw to flow through the transistor 11 a andtransistor 11 c. Thus, the gate-source voltage of the transistor 11 a issuch that allows I1 to flow.

The second timing is the one when the transistor 11 a and transistor 11c are closed and the transistor 11 d is opened. The equivalent circuitavailable at this time is shown in FIG. 3(b). The source-gate voltage ofthe transistor 11 a is maintained. In this case, since the transistor 11a always operates in a saturation region, the current Iw remainsconstant.

Results of this operation are shown in FIG. 5. Specifically, referencenumeral 51 a in FIG. 5(a) denotes a pixel (row) (write pixel row)programmed with current at a certain time point in a display screen 50.The pixel row 51 a is non-illuminated (non-display pixel (row)) asillustrated in FIG. 5(b). Other pixels (rows) are display pixels (rows)53 (current flows through the EL elements 15 of the non-pixels 53 in thedisplay area 53, causing the EL elements 15 to emit light).

In the pixel configuration in FIG. 1, the programming current Iw flowsthrough the source signal line 18 during current programming as shown inFIG. 3(a). The current Iw flows through the transistor 11 a and voltageis set (programmed) in the capacitor 19 in such a way as to maintain thecurrent Iw. At this time, the transistor 11 d is open (off).

During a period when the current flows through the EL element 15, thetransistors 11 c and 11 b turn off and the transistor 11 d turns on asshown in FIG. 3(b). Specifically, a turn-off voltage (Vgh) is applied tothe gate signal line 17 a, turning off the transistors 11 b and 11 c. Onthe other hand, a turn-on voltage (Vgl) is applied to the gate signalline 17 b, turning on the transistor 11 d.

A timing chart is shown in FIG. 4. The subscripts in brackets in FIG. 4(e.g., (1)) indicate pixel row numbers. Specifically, a gate signal line17 a(1) denotes a gate signal line 17 a in a pixel row (1). Also, *H(where “*” is an arbitrary symbol or numeral and indicates a horizontalscanning line number) in the top row in FIG. 4 indicates a horizontalscanning period. Specifically, 1H is a first horizontal scanning period.Incidentally, the items (1H number, 1-H cycle, order of pixel rownumbers, etc.) described above are intended to facilitate explanationand are not intended to be restrictive.

As can be seen from FIG. 4, in each selected pixel row (it is assumedthat the selection period is 1 H), when a turn-on voltage is applied tothe gate signal line 17 a, a turn-off voltage is applied to the gatesignal line 17 b. During this period, no current flows through the ELelement 15 (non-illuminated). In non-selected pixel rows, a turn-offvoltage is applied to the gate signal line 17 a and a turn-on voltage isapplied to the gate signal line 17 b. During this period, a currentflows through the EL element 15 (illuminated).

Incidentally, the gate of the transistor 11 a and gate of the transistor11 c are connected to the same gate signal line 11 a. However, the gateof the transistor 11 a and gate of the transistor 11 c may be connectedto different gate signal lines 11 (see FIG. 32). Then, one pixel willhave three gate signal lines (two in the configuration in FIG. 1). Bycontrolling ON/OFF timing of the gate of the transistor 11 b and ON/OFFtiming of the gate of the transistor 11 c separately, it is possible tofurther reduce variations in the current value of the EL element 15 dueto variations in the transistor 11 a.

By sharing the gate signal line 17 a and gate signal line 17 b and usingdifferent conductivity types (N-channel and P-channel) for thetransistors 11 c and 11 d, it is possible to simplify the drive circuitand improve the aperture ratio of pixels.

With this configuration, a write paths from signal lines are turned offaccording to operation timing of the present invention That is, when apredetermined current is stored, an accurate current value is not storedin a capacitance (capacitor) between the source (S) and gate (G) of thetransistor 11 a if a current path is branched. By using differentconductivity types for the transistors 11 c and 11 d and controllingtheir thresholds, it is possible to ensure that when scanning lines areswitched, the transistor 11 d is turned on after the transistor 11 c isturned off.

In that case, however, since the thresholds of the transistors must becontrolled accurately, it is necessary to pay attention to processes.The circuit described above can be implemented using four transistors atthe minimum, but even if more than four transistors including atransistor 11 e are cascaded for more accurate timing control or forreduction of mirror effect (described later), the principle of operationis the same. By adding the transistor 11 e, it is possible to deliverprogramming current to the EL element 15 more precisely via thetransistor 11 c.

Incidentally, the pixel configuration according to the present inventionis not limited to those shown in FIGS. 1 and 2. For example, pixels maybe configured as shown in FIG. 140. FIG. 140 lacks the transistor 11 dunlike the configuration in FIG. 1. Instead, a changeover switch 1401 isformed or placed. The switch 11 d in FIG. 1 functions to turn on and off(pass and shut off) the current delivered from the driver transistor 11a to the EL element 15. As also described in subsequent examples, theon/off control function of the transistor 11 d constitutes an importantpart of the present invention. The configuration in FIG. 140 achievesthe on/off function without using the transistor 11 d.

In FIG. 140, a terminal a of the changeover switch 1401 is connected toanode voltage Vdd. Incidentally, the voltage applied to the terminal ais not limited to the anode voltage Vdd. It may be any voltage that canturn off the current flowing through the EL element 15.

A terminal b of the changeover switch 1401 is connected to cathodevoltage (indicated as ground in FIG. 140). Incidentally, the voltageapplied to the terminal b is not limited to the cathode voltage. It maybe any voltage that can turn on the current flowing through the ELelement 15.

A terminal c of the changeover switch 1401 is connected with a cathodeterminal of the EL element 15. Incidentally, the changeover switch 1401may be of any type as long as it has a capability to turn on and off thecurrent flowing through the EL element 15. Thus, its installationlocation is not limited to the one shown in FIG. 140 and the switch maybe located anywhere on the path through which current is delivered tothe EL element 15. Also, the switch is not limited by its functionalityas long as the switch can turn on and off the current flowing throughthe EL element 15. In short, the present invention can have any pixelconfiguration as long as switching means capable of turning on and offthe current flowing through the EL element 15 is installed on thecurrent path for the EL element 15.

Also, the term “off” here does not mean a state in which no currentflows, but it means a state in which the current flowing through the ELelement 15 is reduced to below normal. The items mentioned above alsoapply to other configurations of the present invention.

The changeover switch 1401 will require no explanation because it can beimplemented easily by a combination of P-channel and N-channeltransistors. For example, it can be implemented by two circuits ofanalog switches. Of course, the changeover switch 1401 can beconstructed of only P-channel or N-channel transistors because it onlyturns off the current flowing through the EL element 15.

When the changeover switch 1401 is connected to the terminal a, the Vddvoltage is applied to the cathode terminal of the EL element 15. Thus,current does not flow through the EL element 15 regardless of thevoltage state of voltage held by the gate terminal G of the drivertransistor 11 a. Consequently, the EL element 15 is non-illuminated.

When the changeover switch 1401 is connected to the terminal b, the GNDvoltage is applied to the cathode terminal of the EL element 15. Thus,current flows through the EL element 15 according to the state ofvoltage held by the gate terminal G of the driver transistor 11 a.Consequently, the EL element 15 is illuminated.

Thus, in the pixel configuration shown in FIG. 140, no switchingtransistor 11 d is formed between the driver transistor 11 a and the ELelement 15. However, it is possible to control the illumination of theEL element 15 by controlling the changeover switch 1401.

In the pixel configurations shown in FIGS. 1, 2, etc., one pixelcontains one driver transistor 11 a. However, the present invention isnot limited to this and one pixel may contain two or more drivertransistors 11 a. An example is shown in FIG. 144, where one pixelcontains two driver transistors 11 a 1 and 11 a 2, whose gate terminalsare connected to a common capacitor 19. By using a plurality of drivertransistors 11 a, it is possible to reduce variations in programmingcurrent. The other part of the configuration is the same as those shownin FIG. 1 and the like, and thus description thereof will be omitted.

In FIGS. 1 and 2, the current outputted by the driver transistor 11 a ispassed through the EL element 15 and turned on and off by the switchingtransistor 11 d formed between the driver transistor 11 a and the ELelement 15. However, the present invention is not limited to this. Forexample, another configuration is illustrated in FIG. 145.

In the example shown in FIG. 145, the current delivered to the ELelement 15 is controlled by the driver transistor 11 a. The currentflowing through the EL element 15 is turned on and off by the transistor11 d placed between the Vdd terminal and EL element 15. Thus, accordingto the present invention, the transistor 11 d may be placed anywhere aslong as it can control the current flowing through the EL element 15.

Variations in the characteristics of the transistor 11 a are correlatedto the transistor size. To reduce the variations in the characteristics,preferably the channel length of the first transistor 11 a is from 5 μmto 100 μm (both inclusive). More preferably, it is from 10 μm to 50 μm(both inclusive). This is probably because a long channel length Lincreases grain boundaries contained in the channel, reducing electricfields, and thereby suppressing kink effect.

Thus, according to the present invention, circuit means which controlsthe current flowing through the EL element 15 is constructed, formed, orplaced on the path along which current flows into the EL element 15 andthe path along which current flows out of the EL element 15 (i.e., thecurrent path for the EL element 15).

Incidentally, the configuration for use to control the path along whichcurrent flows into the EL element 15 is not limited to the pixelconfiguration in current-programming mode shown in FIG. 1, 140, or thelike. For example, the pixel configuration in voltage-programming modeshown in FIG. 141 can also be used. In FIG. 141, placement of thetransistor 11 d between the EL element 15 and driver transistor 11 amakes it possible to control the current flowing through the EL element15. Of course, the switching circuit 1401 may be placed as shown in FIG.140.

Further, even in the case of current mirroring, a type of currentprogramming, by forming or placing a transistor 11 g as a switchingelement between the driver transistor 11 b and EL element 15 as shown inFIG. 142, it is possible to turn on and off (control) the currentflowing through the EL element 15. Of course, the transistor 11 g may besubstituted with the changeover switch 1401 in FIG. 140.

Incidentally, although the switching transistors 11 d and 11 c in FIG.142 are connected to a single gate signal line 17 a, the switchingtransistor 11 c may be controlled by a gate signal line 17 a 1 and theswitching transistor 11 d may be controlled by a gate signal line 17 a 2as shown in FIG. 143. The configuration in FIG. 143 makes pixel 16control more versatile.

As shown in FIG. 42(a), the transistors 11 b and 11 c may be N-channeltransistors. Also, as shown in FIG. 42(b), the transistors 11 c and 11 dmay be P-channel transistors.

An object of the present invention is to propose a circuit configurationin which variations in transistor characteristics do not affect display.Four or more transistors are required for that. When determining circuitconstants using transistor characteristics, it is difficult to determineappropriate circuit constants unless the characteristics of the fourtransistors are not consistent. Both thresholds of transistorcharacteristics and mobility of the transistors vary depending onwhether the channel direction is horizontal or vertical with respect tothe longitudinal axis of laser irradiation. Incidentally, variations aremore of the same in both cases. However, the mobility and averagethreshold vary between the horizontal direction and vertical direction.Thus, it is desirable that all the transistors in a pixel have the samechannel direction.

Also, if the capacitance value of the storage capacitance 19 is Cs andthe turn-off current value of the second transistor 11 b is Ioff,preferably the following equation is satisfied.3<Cs/Ioff<24More preferably the following equation is satisfied.6<Cs/Ioff<18

By setting the turn-off current of the transistor 11 b to 5 pA or less,it is possible to reduce changes in the current flowing through the ELto 2% or less. This is because when leakage current increases, electriccharges stored between the gate and source (across the capacitor) cannotbe held for one field with no voltage applied. Thus, the larger thestorage capacity of the capacitor 19, the larger the permissible amountof the turn-off current. By satisfying the above equation, it ispossible to reduce fluctuations in current values between adjacentpixels to 2% or less.

Also, preferably transistors composing an active matrix are p-channelpolysilicon thin-film transistors and the transistor 11 b is a dual-gateor multi-gate transistor. As high an ON/OFF ratio as possible isrequired of the transistor 11 b, which acts as a source-drain switch forthe transistor 11 a. By using a dual-gate or multi-gate structure forthe transistor 11 b, it is possible to achieve a high ON/OFF ratio.

The semiconductor films composing the transistors 11 in the pixel 16 aregenerally formed by laser annealing in low-temperature polysilicontechnology. Variations in laser annealing conditions result invariations in transistor 11 characteristics. However, if thecharacteristics of the transistors 11 in the pixel 16 are consistent, itis possible to drive the pixel using current programming such as the oneshown in FIG. 1 so that a predetermined current will flow through the ELelement 15. This is an advantage lacked by voltage programming.Preferably the laser used is an excimer laser.

Incidentally, the semiconductor film formation according to the presentinvention is not limited to the laser annealing method. The presentinvention may also use a heat annealing method and a method whichinvolves solid-phase (CGS) growth. Besides, the present invention is notlimited to the low-temperature polysilicon technology and may usehigh-temperature polysilicon technology.

To deal with this problem, the present invention moves a laser spot(laser irradiation range) 72 in parallel to the source signal line 18 asshown in FIG. 7. Also, the laser spot 72 is moved in such a way as toalign with one pixel row. Of course, the number of pixel rows is notlimited to one. For example, laser may be shot by treating RGB in FIG.72 (three pixel columns in this case) as a single pixel 16. Also, lasermay be directed at two or more pixels at a time. Needless to say, movinglaser irradiation ranges may overlap (it is usual for moving laserirradiation ranges to overlap).

Pixels are constructed in such a way that three pixels of RGB will forma square shape. Thus, each of the R, G, B pixels has oblong shape.Consequently, by performing annealing using an oblong laser spot 72, itis possible to eliminate variations in the characteristics of thetransistors 11 within each pixel. Also, the characteristics (mobility,Vt, S value, etc.) of the transistors 11 connected to the same sourcesignal line 18 can be made uniform (i.e., although the transistors 11connected to adjacent source signal lines 18 may differ incharacteristics, the characteristics of the transistors 11 connected tothe same source signal line can be made almost equal).

In the configuration shown in FIG. 7, three panels are placed lengthwisewithin the length of the laser spot 72. An annealing apparatus whichemits the laser spot 72 recognizes positioning markers 73 a and 73 b ona glass substrate 74 (automatic positioning based on patternrecognition) and moves the laser spot 72. The positioning markers 73 arerecognized by a pattern recognition apparatus. The annealing apparatus(not shown) recognizes the positioning markers 73 and determines thelocation of the pixel column (makes the laser irradiation range 72parallel to the source signal line 18). It emits the laser spot 72 insuch a way as to overlap with the location of each pixel column forsequential annealing.

Preferably, the laser annealing method (which involves emitting a linearlaser spot in parallel to the source signal line 18) described withreference to FIG. 7 is used for current programming of an organic ELdisplay panel, in particular. This is because the transistors 11 placedin the direction parallel to the source signal line have the samecharacteristics (the characteristics of the pixel transistors adjacentin the longitudinal direction are quite similar to each other). Thisreduces changes in the voltage level of the source signal lines when thepixels are driven by current, and thus reduces the chances ofinsufficient write current.

For example, in the case of white raster display, since almost the samecurrent is passed through the transistors 11 a in adjacent pixels, thecurrent outputted from the source driver IC 14 does not have significantamplitude changes. If the transistors 11 a in FIG. 1 have the samecharacteristics and the currents used for current programming of pixelshave the same value within the pixel column, the potential of the sourcesignal line 18 during the current programming is constant. Thus, nopotential fluctuation occurs in the source signal line 18. If thetransistors 11 a connected to the same source signal line 18 have almostthe same characteristics, there should be no significant potentialfluctuation in the source signal line 18. This is also true to othercurrent-programmable pixel configurations such as the one shown in FIG.38 (thus, it is preferable to use the manufacturing method shown in FIG.7).

A method which involves programming two or more pixel rowssimultaneously and which are described with reference to FIGS. 27, 30,etc. can achieve a uniform image display (because the method is notprone to display irregularities due mainly to variations in transistorcharacteristics) In the case of FIG. 27, etc., since a plurality ofpixel rows are selected simultaneously, if the transistors in adjacentpixel rows are uniform, irregularities in the characteristics of thetransistors placed in the lengthwise direction can be absorbed by thesource driver circuit 14.

Incidentally, although an IC chip is illustrated in FIG. 7 as beingstacked on the source driver circuit 14, this is not restrictive and itgoes without saying that the source driver circuit 14 may be formed inthe same process as the pixel 16.

The present invention, in particular, ensures that a voltage thresholdVth2 of the driver transistor 11 b will not fall below a voltagethreshold Vth1 of the corresponding driver transistor 11 a in the pixel.For example, gate length L2 of the transistor 11 b is made longer thangate length L1 of the transistor 11 a so that Vth2 will not fall belowVth1 even if process parameters of these thin-film transistors change.This makes it possible to suppress subtle current leakage.

Incidentally, the items mentioned above also apply to pixelconfiguration of a current mirror shown in FIG. 38. The pixel in FIG. 38consists of a driver transistor 11 a through which a signal currentflows, a driver transistor 11 b which controls drive current flowingthrough a light-emitting element such as an EL element 15, a transistor11 c which connects or disconnects a pixel circuit and data line “data”by controlling a gate signal line 17 a 1, a switching transistor 11 dwhich shorts the gate and drain of the transistor 11 a during a writeperiod by controlling a gate signal line 17 a 2, a capacitance C19 whichholds gate-source voltage of the transistor 11 a after application ofvoltage, the EL element 15 serving as a light-emitting element, etc.

In FIG. 38, the transistors 11 c and 11 d are N-channel transistors andother transistors are P-channel transistors, but this is only exemplaryand are not restrictive. A capacitance Cs has its one end connected tothe gate of the transistor 11 a, and the other end to Vdd (power supplypotential), but it may be connected to any fixed potential instead ofVdd. The cathode (negative pole) of the EL element 15 is connected tothe ground potential.

Next, the EL display panel or EL display apparatus of the presentinvention will be described. FIG. 6 is an explanatory diagram whichmainly illustrates a circuit of the EL display apparatus. Pixels 16 arearranged or formed in a matrix. Each pixel 16 is connected with a sourcedriver circuit 14 which outputs current for use in current programmingof the pixel. In an output stage of the source driver circuit 14 arecurrent mirror circuits (described later) corresponding to the bit countof a video signal. For example, if 64 gradations are used, 63 currentmirror circuits are formed on respective source signal lines so as toapply desired current to the source signal lines 18 when an appropriatenumber of current mirror circuits is selected (see FIG. 64).

Incidentally, the minimum output current of one current mirror circuitis from 10 nA to 50 nA (both inclusive). Preferably, the minimum outputcurrent of the current mirror circuit should be from 15 nA to 35 nA(both inclusive) to secure accuracy of the transistors composing thecurrent mirror circuit in the source driver IC 14.

Besides, a precharge or discharge circuit is incorporated to charge ordischarge the source signal line 18 forcibly. Preferably, voltage(current) output values of the precharge or discharge circuit whichcharges or discharges the source signal line 18 forcibly can be setseparately for R, G, and B. This is because the thresholds of the ELelement 15 differ among R, G, and B (regarding the precharge circuitrefer to FIGS. 70 and 173 and its explanation).

Organic EL elements are known to have heavy temperature dependence(temperature characteristics). To adjust changes in emission brightnesscaused by the temperature characteristics, reference current is adjusted(varied) in an analog fashion by adding nonlinear elements such asthermistors or posistors to the current mirror circuits to vary outputcurrent and adjusting the changes due to the temperature characteristicswith the thermistors or the like.

According to the present invention, the source driver 14 is made of asemiconductor silicon chip and connected with a terminal on the sourcesignal line 18 of the board 71 by glass-on-chip (COG) technology. Thesource driver 14 can be mounted not only by the COG technology. It isalso possible to mount the source driver circuit 14 by chip-on-film(COF) technology and connect it to the signal lines of the displaypanel. Regarding the driver IC, it may be made of three chips byconstructing a power supply IC 82 separately.

Panel is tested before the source driver IC 14 is mounted. The test isconducted by applying a constant current to the source signal lines 18.

The constant current is applied by attaching lead wires 2271 to the pads1522 formed on the ends of the source signal lines 18 and forming testpads 2272 on their ends as illustrated in FIG. 227.

By forming the test pads 2272, it is possible to conduct the testwithout using the pads 1522.

After the source driver IC 14 is mounted on the substrate 71, itsperiphery is sealed with sealing resin 2281 as illustrated in FIG. 228.

On the other hand, the gate driver circuit 12 is formed bylow-temperature polysilicon technology. That is, it is formed in thesame process as the transistors in pixels. This is because the gatedriver 12 has a simpler internal structure and lower operating frequencythan the source driver circuit 14. Thus, it can be formed easily even bylow-temperature polysilicon technology and allows bezel width to bereduced. Of course, it is possible to construct the gate driver circuit12 from a silicon chip and mount it on the board 71 using the COGtechnology. Also, switching elements such as pixel transistors as wellas gate drivers may be formed by high-temperature polysilicon technologyor may be formed of an organic material (organic transistors).

The gate driver 12 incorporates a shift register circuit 61 a for a gatesignal line 17 a and a shift register circuit 61 b for a gate signalline 17 b. The shift register circuits 61 are controlled bypositive-phase and negative-phase clock signals (CLKxP and CLKxN) and astart pulse (STx) (see FIG. 6). Besides, it is preferable to add anenable (ENABL) signal which controls output and non-output from the gatesignal line and an up-down (UPDWN) signal which turns a shift directionupside down. Also, it is preferable to install an output terminal toensure that the start pulse is shifted by the shift register and isoutputted. Incidentally, shift timings of the shift registers arecontrolled by a control signal from a control IC 81 (see FIGS. 8 and208). Also, the gate driver circuit 12 incorporates a level shiftcircuit which level-shifts external data.

Since the shift register circuits 61 have small buffer capacity, theycannot drive the gate signal lines 17 directly. Therefore, at least twoor more inverter circuits 62 are formed between each shift registercircuit 61 and an output gate 63 which drives the gate signal line 17(see FIG. 204).

The same applies to cases in which the source driver 14 is formed on theboard 71 by polysilicon technology such as low-temperature polysilicontechnology. A plurality of inverter circuits are formed between ananalog switching gate such as a transfer gate which drives the sourcesignal line 18 and the shift register of the source driver circuit 14.The following matters (shift register output and output stages whichdrive signal lines (inverter circuits placed between output stages suchas output gates or transfer gates) are common to the gate driver circuitand source driver circuit.

For example, although the output from the source driver 14 is shown inFIG. 6 as being connected directly to the source signal line 18,actually the output from the shift register of the source driver isconnected with multiple stages of inverter circuits, and the inverteroutputs are connected to analog switching gates such as transfer gates.

The inverter circuit 62 consists of a P-channel MOS transistor andN-channel MOS transistor. As described earlier, the shift registercircuit 61 of the gate driver circuit 12 has its output end connectedwith multiple stages of inverter circuits 62 and the final output isconnected to the output gate 63. Incidentally, the inverter circuit 62may be composed solely of P-channel MOS transistors. In that case,however, the circuit may be configured simply as a gate circuit ratherthan an inverter.

FIG. 8 is a block diagram of signal and voltage supplies on a displayapparatus according to the present invention or a block diagram of thedisplay apparatus. Signals (power supply wiring, data wiring, etc.) aresupplied from the control IC 81 to a source driver circuit 1 a via aflexible board 84.

In FIG. 8, a control signal for the gate driver 12 is generated by thecontrol IC, level-shifted by the source driver 14, and applied to thegate driver 12. Since drive voltage of the source driver 14 is 4 to 8(V), the control signal with an amplitude of 3.3 (V) outputted from thecontrol IC 81 can be converted into a signal with an amplitude of 5 (V)which can be received by the gate driver 12.

In FIG. 8 and the like, what is denoted by reference numeral 14 has beendescribed as a source driver, but instead of being a mere driver, it mayincorporate a power circuit, buffer circuit (including a circuit such asa shift register), data conversion circuit, latch circuit, commanddecoder, shifting circuit, address conversion circuit, image memory,etc. Needless to say, a three-side free configuration or otherconfiguration, drive system, etc. described with reference to FIG. 9 andthe like are also applicable to the configuration described withreference to FIG. 8 and the like.

When the display panel is used for information display apparatus such asa cell phone, it is preferable to mount (form) the source driver IC(circuit) 14 and gate driver IC (circuit) 12 on one side of the displaypanel as shown in FIG. 9 (incidentally, a configuration in which driverICs (circuits) are mounted (formed) on one side of a display panel isreferred to as a three-side free configuration (structure).Conventionally, the gate driver IC 12 is mounted on an X side of adisplay area and a source driver IC 14 is mounted on a Y side). Thismakes it easy in the design to center the center line of a displayscreen 50 on the display apparatus and mount the driver ICs. Using thethree-side free configuration, the gate driver circuit may be producedby high-temperature polysilicon technology, low-temperature polysilicontechnology or the like (i.e., at least one of the source driver circuit14 and gate driver circuit 12 may be formed directly on the board 71 bypolysilicon technology).

Incidentally, the three-side free configuration includes not only aconfiguration in which ICs are placed or formed directly on the board71, but also a configuration in which a film (TCP, TAB, or othertechnology) with a source driver IC (circuit) 14 and gate driver IC(circuit) 12 mounted are pasted on one side (or almost one side) of theboard 71. That is, the three-side free configuration includesconfigurations and arrangements in which two sides are left free of ICsand all similar configurations.

If the gate driver circuit 12 is placed beside the source driver circuit14 as shown in FIG. 9, the gate signal line 17 must be formed along theside C.

Incidentally, the thick solid line in FIG. 9, etc. indicates gate signallines 17 formed in parallel. Thus, as many gate signal lines 17 as thereare scanning signal lines are formed in parallel in part b (bottom ofthe screen) while a single gate signal line 17 is formed in part a (topof the screen).

Spacing between the gate signal lines 17 formed on the side C is from 5μm to 12 μm (both inclusive). If it is less than 5 μm, parasiticcapacitance will cause noise on adjacent gate signal lines. It has beenshown experimentally that parasitic capacitance has significant effectswhen the spacing is 7 μm or less. Furthermore, when the spacing is lessthan 5 μm, beating noise and other image noise appear intensely on thedisplay screen. In particular, noise generation differs between theright and left sides of the screen and it is difficult to reduce thebeating noise and other image noise. When the spacing exceeds 12 μm,bezel width D of the display panel becomes too large to be practical.

To reduce the image noise, a ground pattern (conductive pattern whichhas been fixed at a constant voltage or set generally at a stablepotential) can be placed under or above the gate signal lines 17.Alternatively, a separate shield plate (shield foil: a conductivepattern which has been fixed at a constant voltage or set generally at astable potential) may be placed on the gate signal lines 17.

The gate signal lines 17 on the side C in FIG. 9 may be formed of ITOelectrodes. However, to reduce resistance, preferably they are formed bylaminating ITO and thin metal films. Also preferably they are formed ofmetal films. When using an ITO laminate, a titanium film is formed onthe ITO, and a thin aluminum film or aluminum-molybdenum alloy film isformed on it. Alternatively, a chromium is formed on the ITO. For metalfilms, thin aluminum films or chromium films are used. This also appliesto other examples of the present invention.

Incidentally, although it has been stated with reference to FIG. 9 andthe like that the gate signal lines 17 are placed on one side of thedisplay area, this is not restrictive and they may be placed on bothsides. For example, the gate signal line 17 a may be placed (formed) onthe right side of the display screen 50 while the gate signal line 17 bmay be placed (formed) on the left side of the display screen 50. Thisalso applies to other examples.

Also, the source driver IC 14 and gate driver IC 12 may be integratedinto a single chip. Then, it suffices to mount only one IC chip on thedisplay panel. This also reduces implementation costs. Furthermore, thismakes it possible to simultaneously generate various voltages for use inthe single-chip driver IC.

Incidentally, although it has been stated that the source driver IC 14and gate driver IC 12 are made of silicon or other semiconductor wafersand mounted on the display panel, this is not restrictive. Needless tosay, they may be formed directly on the display panel 82 usinglow-temperature polysilicon technology or high-temperature polysilicontechnology.

Although it has been stated that pixels are of the three primary colorsof R, G, and B, this is not restrictive. They may be of three colors ofcyan, yellow, and magenta. They may be of two colors of B and yellow. Ofcourse, they may be monochromatic. Alternatively, they may be of sixcolors of R, G, B, cyan, yellow, and magenta or of five colors of R, G,B, cyan, and magenta. These are natural colors which provide an expandedcolor reproduction range, enabling good display. Thus, the EL displayapparatus according to the present invention is not limited to thosewhich provide color display using the three primary colors of R, G, andB.

Mainly three methods are available to colorize an organic EL displaypanel. One of them is a color conversion method. It suffices to form asingle layer of blue as a light-emitting layer. The remaining green andred colors needed for full color display can be produced from the bluecolor through color conversion. Thus, this method has the advantage ofeliminating the need to paint the R, G, and B colors separately andprepare organic EL materials for the R, G, and B colors. The colorconversion method does not lower yields unlike the multi-color paintingmethod. Any of the three methods can be applied to the EL display panelof the present invention.

Also, in addition to the three primary colors, white light-emittingpixels may be formed. The white light-emitting pixels can be created(formed or constructed) by laminating R, G, and B light-emittingstructures. A set of pixels consists of pixels for the three primarycolors RGB and a white light-emitting pixel 16W. Forming the whitelight-emitting pixels makes it easier to express peak brightness ofwhite, and thus possible to implement bright image display.

Even when using a set of pixels for the three primary colors RGB, it ispreferable to vary pixel electrode areas for the different colors. Ofcourse, an equal area may be used if luminous efficiencies of thedifferent colors as well as color purity are well balanced. However, ifone or more colors are poorly balanced, preferably the pixel electrodes(light-emitting areas) are adjusted. The electrode area for each colorcan be determined based on current density. That is, when white balanceis adjusted in a color temperature range of 7000 K (Kelvin) to 12000 K(both inclusive), difference between current densities of differentcolors should be within ±30%. More preferably, the difference should bewithin ±15%. For example, if current densities are around 100 A/squaremeter, all the three primary colors should have a current density of 70A/square meter to 130 A/square meter (both inclusive). More preferably,all the three primary colors should have a current density of 85A/square meter to 115 A/square meter (both inclusive).

The EL element 15 is a self-luminous element. When light from thisself-luminous element enters a transistor serving as a switchingelement, a photoconductive phenomenon occurs. The photoconductivephenomenon is a phenomenon in which leakage (off-leakage) increases dueto photoexcitation when a switching element such as a transistor is off.

To deal with this problem, the present invention forms a shading filmunder the gate driver 12 (source driver 14 in some cases) and under thepixel transistor 11. The shading film is formed of thin film of metalsuch as chromium and is from 50 nm to 150 nm thick (both inclusive). Athin film will provide a poor shading effect while a thick film willcause irregularities, making it difficult to pattern the transistor 11A1in an upper layer.

In the case of the driver circuit 12 and the like, it is necessary toreduce penetration of light not only from the topside, but also from theunderside. This is because the photoconductive phenomenon will causemalfunctions. If cathode electrodes are made of metal films, the presentinvention also forms a cathode electrode on the surface of the driver 12and the like and uses it as a shading film.

However, if a cathode electrode is formed on the driver 12, electricfields from the cathode electrode may cause driver malfunctions or placethe cathode electrode and driver circuit in electrical contact. To dealwith this problem, the present invention forms at least one layer oforganic EL film, and preferably two or more layers, on the drivercircuit 12 simultaneously with the formation of organic EL film on thepixel electrode.

If a short circuit occurs between terminals of one or more transistors11 or between a transistor 11 and signal line in the pixel, the ELelement 15 may become a bright spot which remains illuminatedconstantly. The bright spot is visually conspicuous and must be turnedinto a black spot (turned off). The pixel 16 which corresponds to thebright spot is detected and the capacitor 19 is irradiated with laserlight to cause a short circuit across the capacitor. As a result, thecapacitor 19 can no longer hold electric charges, and thus thetransistor 11 a can be stopped from passing current. It is desirable toremove that part of a cathode film which will be irradiated with laserlight to prevent the laser irradiation from causing a short circuitbetween a terminal electrode of the capacitor 19 and the cathode film.

Flaws in a transistor 11 in the pixel 16 will affect the source driverIC 14 and the like. For example, if a source-drain (SD) short circuit562 occurs in the driver transistor 11 a in FIG. 56, a Vdd voltage ofthe panel is applied to the source driver IC 14. Thus, preferably thepower supply voltage of the source driver IC 14 is kept equal to orhigher than the power supply voltage Vdd of the panel. Preferably, thereference voltage used by the source driver IC 14 can be adjusted withan electronic regulator 561 (See FIG. 148).

If an SD short circuit 562 occurs in the transistor 11 a, an excessivecurrent flows through the EL element 15. In other words, the EL element15 remains illuminated constantly (becomes a bright spot). The brightspot is conspicuous as a defect. For example, if a source-drain (SD)short circuit occurs in the transistor 11 a in FIG. 56, current flowsconstantly from the Vdd voltage to the EL element 15 (when thetransistor 11 d is on) regardless of the magnitude of gate (G) terminalvoltage of the transistor 11 a. Thus, a bright spot results.

On the other hand, if an SD short circuit occurs in the transistor 11 aand if the transistor 11 c is on, the Vdd voltage is applied to thesource signal line 18 and to the source driver 14. If the power supplyvoltage of the source driver 14 is not higher than Vdd, voltageresistance may be exceeded, causing the source driver 14 to rupture.Thus, it is preferable that the power supply voltage of the sourcedriver 14 is equal to or higher than the Vdd voltage (the higher voltageof the panel).

An SD short circuit of the transistor 11 a may go beyond a point defectand lead to rupture of the source driver circuit of the panel. Also, thebright spot is conspicuous, which makes the panel defective. Thus, it isnecessary to turn the bright spot into a black spot by cutting thewiring which connects between the transistor 11 and EL element 15.Preferably an optical means such as laser light is used to cut thewiring.

A drive method according to the present invention will be describedbelow. As shown in FIG. 1, the gate signal line 17 a conducts when therow remains selected (since the transistor 11 in FIG. 1 is a P-channeltransistor, the gate signal line 17 a conducts when it is in low state)and the gate signal line 17 b conducts when the row remainsnon-selected.

Parasitic capacitance (not shown) is present in the source signal line18. The parasitic capacitance is caused by the capacitance at thejunction of the source signal line 18 and gate signal line 17, channelcapacitance of the transistors 11 b and 11 c, etc.

The time t required to change the current value of the source signalline 18 is given by t=C·V/I, where C is stray capacitance, V is avoltage of the source signal line, and I is a current flowing throughthe source signal line. Thus, if the current value can be increasedtenfold, the time required to change the current value can be reducednearly tenfold. This also means that the current value can be changed toa predetermined value even if the parasitic capacitance of the sourcesignal line 18 is increased tenfold. Thus, to apply a predeterminedcurrent value during a short horizontal scanning period, it is useful toincrease the current value.

When input current is increased tenfold, output current is alsoincreased tenfold, resulting in a tenfold increase in the EL brightness.Thus, to obtain predetermined brightness, a light emission period isreduced tenfold by reducing the conduction period of the transistor 17 din FIG. 1 tenfold compared to a conventional conduction period.Incidentally, the tenfold increases/decreases are cited as an example tofacilitate understanding and are not meant to be restrictive.

Thus, in order to charge and discharge the parasitic capacitance of thesource signal line 18 sufficiently and program a predetermined currentvalue into the transistor 11 a of the pixel 16, it is necessary tooutput a relatively large current from the source driver 14. However,when such a large current is passed through the source signal line 18,its current value is programmed into the pixel and a current larger thanthe predetermined current flows through the EL element 15. For example,if a 10 times larger current is programmed, naturally a 10 times largercurrent flows through the EL element 15 and the EL element 15 emits 10times brighter light. To obtain predetermined emission brightness, thetime during which the current flows through the EL element 15 can bereduced tenfold. This way, the parasitic capacitance can becharged/discharged sufficiently from the source signal line 18 and thepredetermined emission brightness can be obtained.

Incidentally, although it has been stated that a 10 times larger currentvalue is written into the pixel transistor 11 a (more precisely, theterminal voltage of the capacitor 19 is set) and that the conductionperiod of the EL element 15 is reduced to 1/10, this is only exemplary.In some cases, a 10 times larger current value may be written into thepixel transistor 11 a and the conduction period of the EL element 15 maybe reduced to ⅕. On the other hand, a 10 times larger current value maybe written into the pixel transistor 11 a and the conduction period ofthe EL element 15 may be halved.

The present invention is characterized in that the write current into apixel is set at a value other than a predetermined value and that acurrent is passed through the EL element 15 intermittently. For ease ofexplanation, it has been stated herein that an N times larger current iswritten into the pixel transistor 11 and the conduction period of the ELelement 15 is reduced to 1/N. However, this is not restrictive. Needlessto say, N1 times larger current may be written into the pixel transistor11 and the conduction period of the EL element 15 maybe reduced to 1/N2(N1 and N2 are different from each other)

In white raster display, it is assumed that average brightness over onefield (frame) period of the display screen 50 is B0. This drive methodperforms current (voltage) programming in such a way that the brightnessB1 of each pixel 16 is higher than the average brightness B0. Also, anon-display area 53 appears during at least one field (frame) period.Thus, in the drive method according to the present invention, theaverage brightness over one field (frame) period is lower than B1.

Incidentally, the non-display area 52 and display area 53 are notnecessarily spaced equally. For example, they may appear at random(provided that the display period or non-display period makes up apredetermined value (constant ratio) as a whole). Also, display periodsmay vary among R, G, and B.

That is, display periods of R, G, and B or non-display periods can beadjusted (set) to predetermined values (proportions) in such a way as toobtain an optimum white balance.

To facilitate explanation of the drive method according to the presentinvention, it is assumed that “1/N” means reducing 1F (one field or oneframe) to 1/N. Needless to say, however, it takes time to select onepixel row and to program current values (normally, one horizontalscanning period (1 H)) and error may result depending on scanningconditions.

For example, the EL element 15 may be illuminated for ⅕ of a period byprogramming the pixel 16 with an N=10 times larger current. The ELelement 15 illuminates 10/5=2 times more brightly. It is also possibleto program an N=2 times larger current into the pixel 16 and illuminatethe EL element 15 for ¼ of the period. The EL element 15 illuminates2/4=0.5 time more brightly. In short, the present invention achievesdisplay other than constant display (1/1, i.e., non-intermittentdisplay) by using a current other than an N=1 time current for currentprogramming. Also, the drive system turns off the current supplied tothe EL element 15, at least once during one frame (or one field) period.Also, the drive system at least achieves intermittent display byprogramming the pixel 16 with a current larger than a predeterminedvalue.

A problem with an organic (inorganic) EL display is that it uses adisplay method basically different from that of an CRT or other displaywhich presents an image as a set of displayed lines using an electrongun. That is, the EL display holds the current (voltage) written into apixel for 1F (one field or one frame) period. Thus, a problem is thatdisplaying moving pictures will result in blurred edges.

According to the present invention, current is passed through the ELelement 15 only for a period of 1F/N, but current is not passed duringthe remaining period (1F(N−1)/N). Let us consider a situation in whichthe drive system is implemented and one point on the screen is observed.In this display condition, image data display and black display(non-illumination) are repeated every 1F. That is, image data isdisplayed intermittently in the temporal sense. When moving picture dataare displayed intermittently, a good display condition is achievedwithout edge blur. In short, movie display close to that of a CRT can beachieved.

The drive method according to the present invention implementsintermittent display. However, the intermittent display can be achievedby simply turning on and off the transistor 11 d on a 1-H cycle.Consequently, a main clock of the circuit does not differ fromconventional ones, and thus there is no increase in the powerconsumption of the circuit. Liquid crystal display panels need an imagememory in order to achieve intermittent display. According to thepresent invention, image data is held in each pixel 16. Thus, thepresent invention requires no image memory for intermittent display.

The present invention controls the current passed through the EL element15 by simply turning on and off the switching transistor 11 d, thetransistor 11 e, and the like. That is, even if the current Iw flowingthrough the EL element 15 is turned off, the image data is held as it isin the capacitor 19. Thus, when the transistor 11 d is turned on thenext time, the current passed through the EL element 15 has the samevalue as the current flowing through the EL element 15 the previoustime. Even to achieve black insertion (intermittent display such asblack display), the present invention does not need to speed up the mainclock of the circuit. Also, it does not need to elongate a time axis,and thus requires no image memory. Besides, the EL element 15 respondsquickly, requiring a short time from application of current to lightemission. Thus, the present invention is suitable for movie display, andby using intermittent display, it can solve a problem with conventionaldata-holding display panels (liquid crystal display panels, EL displaypanels, etc.) in displaying moving pictures.

Furthermore, in a large display apparatus, if increased wiring length ofthe source signal line 18 results in increased parasitic capacitance inthe source signal line 18, this can be dealt with by increasing thevalue of N. When the value of programming current applied to the sourcesignal line 18 is increased N times, the conduction period of the gatesignal line 17 b (the transistor 11 d) can be set to 1F/N. This makes itpossible to apply the present invention to television sets, monitors,and other large display apparatus.

The output stage of the source driver circuit 14 is constituted of aconstant-current circuit 704 (see FIG. 70). The constant-current circuiteliminates the need to vary buffer size of the output stage according tothe size of the display panel unlike the source driver circuits ofliquid crystal display panels.

The drive method according to the present invention will be describedwith reference to drawings in more detail below. The parasiticcapacitance of the source signal line 18 is generated by the couplingcapacitance with adjacent source signal lines 18, buffer outputcapacitance of the source driver IC (circuit) 14, cross capacitancebetween the source signal line 18 and gate signal line 17, etc. Thisparasitic capacitance is normally 10 pF or larger. In the case ofvoltage driving, since voltage is applied to the source signal line 18from the source driver IC 14 at low impedance, more or less largeparasitic capacitance does not disturb driving.

However, in the case of current driving, especially image display at theblack level, the pixel capacitor 19 needs to be programmed with a minutecurrent of 20 nA or less. Thus, if parasitic capacitance larger than apredetermined value is generated, the parasitic capacitance cannot becharged and discharged during the time when one pixel row is programmed(normally within 1 H, but not limited to 1 H because two pixel rows maybe programmed simultaneously). If the parasitic capacitance cannot becharged and discharged within a period of 1 H, sufficient current cannotbe written into the pixel, resulting in inadequate resolution.

In the pixel configuration in FIG. 1, the programming current Iw flowsthrough the source signal line 18 during current programming as shown inFIG. 3(a). The current Iw flows through the transistor 11 a and voltageis set (programmed) in the capacitor 19 in such a way as to maintain thecurrent Iw. At this time, the transistor 11 d is open (off).

During a period when the current flows through the EL element 15, thetransistors 11 c and 11 b turn off and the transistor 11 d turns on asshown in FIG. 3(b). Specifically, a turn-off voltage (Vgh) is applied tothe gate signal line 17 a, turning off the transistors 11 b and 11 c. Onthe other hand, a turn-on voltage (Vgl) is applied to the gate signalline 17 b, turning on the transistor 11 d.

Suppose a current I1 is N times the current which should normally flow(a predetermined value), the current flowing through the EL element 15in FIG. 3(b) is also Iw. Thus, the EL element 15 emits light 10 timesmore brightly that a predetermined value. In other words, as shown inFIG. 12, the larger the magnification N, the higher the displaybrightness B of the pixel 16. Thus, the magnification N and thebrightness of the pixel 16 are proportional to each other.

If the transistor 11 d is kept on for a period 1/N the period duringwhich it is normally kept on (approximately 1F) and is kept off duringthe remaining period (N−1)/N, the average brightness over the 1F equalspredetermined brightness. This display condition closely resembles thedisplay condition under which a CRT is scanning a screen with anelectronic gun. The difference is that 1/N of the entire screenilluminates (where the entire screen is taken as 1) (in a CRT, whatilluminates is one pixel row—more precisely, one pixel).

According to the present invention, 1F/N of the image display area 53moves from top to bottom of the screen 50 as shown in FIG. 13(b).According to the present invention, current flows through the EL element15 only for the period of 1F/N, but current does not flow during theremaining period (1F(N−1)/N). Thus, the pixel is displayedintermittently. However, due to an afterimage, the entire screen appearsto be displayed uniformly to the human eye.

Incidentally, as shown in FIG. 13, the write pixel row 51 a isnon-illuminated 52 a. However, this is true only to the pixelconfigurations in FIGS. 1, 2, etc. In the pixel configuration of acurrent mirror shown in FIG. 38, etc., the write pixel row 51 a may beilluminated. However, description will be given herein citing mainly thepixel configuration in FIG. 1 for ease of explanation. A drive methodwhich involves driving a pixel intermittently by programming it with acurrent larger than the predetermined drive current Iw shown in FIGS.13, 16, etc. is referred to as N-fold pulse driving.

In this display condition, image data display and black display(non-illumination) are repeated every 1F. That is, image data isdisplayed at intervals (intermittently) in the temporal sense. Liquidcrystal display panels (EL display panels other than that of the presentinvention), which hold data in pixels for a period of 1F, cannot keep upwith changes in image data during movie display, resulting is blurredmoving pictures (edge blur of images). Since the present inventiondisplays images intermittently, it can achieve a good display conditionwithout edge blur of images. In short, movie display close to that of aCRT can be achieved.

Incidentally, to drive the pixel 16 as shown in FIG. 13, it is necessaryto be able to separately control the current programming period of thepixel 16 (in the configuration shown in FIG. 1, the period during whichthe turn-on voltage Vgl is applied to the gate signal line 17 a) and theperiod when the EL element 15 is under on/off control (in the pixelconfiguration shown in FIG. 1, the period during which the turn-onvoltage Vgl or turn-off voltage Vgh is applied to the gate signal line17 b). Thus, the gate signal line 17 a and gate signal line 17 b must beseparated.

For example, when only a single gate signal line 17 is laid from thegate driver circuit 12 to the pixel 16, the drive method according tothe present invention cannot be implemented using a configuration inwhich logic (Vgh or Vgl) applied to the gate signal line 17 is appliedto the transistor 11 b and the logic applied to the gate signal line 17is converted (Vgh or Vgl) by an inverter and applied to the transistor11 d. Thus, the present invention requires a gate driver circuit 12 awhich operates the gate signal line 17 a and gate driver circuit 12 bwhich operates the gate signal line 17 b.

Besides, the drive method according to the present invention provides anon-illuminated display even with the pixel configuration shown in FIG.1 during periods other than the current programming period (1 H).

A timing chart of the drive method shown in FIG. 13 is illustrated inFIG. 14. The pixel configuration referred to in the present inventionand the like is the one shown in FIG. 1 unless otherwise stated. As canbe seen from FIG. 14, in each selected pixel row (the selection periodis designated as 1 H), when a turn-on voltage (Vgl) is applied to thegate signal line 17 a (see FIG. 14(a)), a turn-off voltage (Vgh) isapplied to the gate signal line 17 b (see FIG. 14(b)). During thisperiod, current does not flow through the EL element 15(non-illumination mode). In a non-selected pixel row, a turn-on voltage(Vgl) is applied to the gate signal line 17 b and a turn-off voltage(Vgh) is applied to the gate signal line 17 a. During this period,current flows through the EL element 15 (illumination mode). In theillumination mode, the EL element 15 illuminates at a brightness (N·B) Ntimes the predetermined brightness and the illumination period is 1F/N.Thus, the average display brightness of the display panel over 1F isgiven by (N·B)×(1/N)=B (the predetermined brightness).

FIG. 15 shows an example in which operations shown in FIG. 14 areapplied to each pixel row. The figure shows voltage waveforms applied tothe gate signal lines 17. Waveforms of the turn-off voltage are denotedby Vgh (high level) while waveforms of the turn-on voltage are denotedby Vgl (low level). The subscripts such as (1) and (2) indicate selectedpixel row numbers.

In FIG. 15, a gate signal line 17 a(1) is selected (Vgl voltage) and aprogramming current flows through the source signal line 18 in thedirection from the transistor 11 a in the selected pixel row to thesource driver circuit 14. The programming current is N times larger thana predetermined value (for ease of explanation, it is assumed that N=10.Of course, since the predetermined value is a data current for use todisplay images, it is not a fixed value unless in the case of whiteraster display). Therefore, the capacitor 19 is programmed so that a 10times larger current will flow through the transistor 11 a. When thepixel row (1) is selected, in the pixel configuration shown in FIG. 1, aturn-off voltage (Vgh) is applied to the gate signal line 17 b(1) andcurrent does not flow through the EL element 15.

After 1 H, a gate signal line 17 a(2) is selected (Vgl voltage) and aprogramming current flows through the source signal line 18 in thedirection from the transistor 11 a in the selected pixel row to thesource driver circuit 14. The programming current is N times larger thana predetermined value (for ease of explanation, it is assumed thatN=10). Therefore, the capacitor 19 is programmed so that 10 times largercurrent will flow through the transistor 11 a. When the pixel row (2) isselected, in the pixel configuration shown in FIG. 1, a turn-off voltage(Vgh) is applied to the gate signal line 17 b(2) and current does notflow through the EL element 15. However, since a turn-off voltage (Vgh)is applied to the gate signal line 17 a(1) and a turn-on voltage (Vgl)is applied to the gate signal line 17 b(1) of the pixel row (1), the ELelement 15 illuminates.

After the next 1 H, a gate signal line 17 a(3) is selected, a turn-offvoltage (Vgh) is applied to the gate signal line 17 b(3), and currentdoes not flow through the EL element 15 in the pixel row (3). However,since a turn-off voltage (Vgh) is applied to the gate signal lines 17a(1) and (2) and a turn-on voltage (Vgl) is applied to the gate signallines 17 b(1) and (2) in the pixel rows (1) and (2), the EL element 15illuminates.

Through the above operation, images are displayed in sync with asynchronization signal of 1 H. However, with the drive method in FIG.15, a 10 times larger current flows through the EL element 15. Thus, thedisplay screen 50 is 10 times brighter. Of course, it goes withoutsaying that for display at a predetermined brightness in this state, theprogramming current can be reduced to 1/10. However, a 10 times smallercurrent will cause a shortage of write current due to parasiticcapacitance. Thus, the basic idea of the present invention is to use alarge current for programming, insert a non-display area 52, and therebyobtain a predetermined brightness.

Incidentally, the drive method according to the present invention causesa current larger than a predetermined current to flow through the ELelement 15, and thereby charges and discharges the parasitic capacitanceof the source signal line 18 sufficiently. That is, there is no need topass an N times larger current through the EL element 15. For example,it is conceivable to form a current path in parallel with the EL element15 (form a dummy EL element and use a shield film to prevent the dummyEL element from emitting light) and divide the flow of current betweenthe EL element 15 and the dummy EL element. For example, when a signalcurrent is 0.2 μA, a programming current is set to 2.2 μA and thecurrent of 2.2 μA is passed through the transistor 11 a. Then, thesignal current of 0.2 μA may be passed through the EL element 15 and 2μA may be passed through the dummy EL element, for example. That is, thedummy pixel row 281 in FIG. 27 remains selected constantly.Incidentally, the dummy pixel row is either kept from emitting light orhidden from view by a shield film or the like even if it emits light.

With the above configuration, by increasing the current passed throughthe source signal line 18 N times, it is possible to pass an N timeslarger current through the driver transistor 11 a and pass a currentsufficiently smaller than the N times larger current through the ELelement 15. As shown in FIG. 5, this method allows the entire displayscreen 50 to be used as the image display area 53 without a non-displayarea 52.

FIG. 13(a) shows writing into the display screen 50. In FIG. 13(a),reference numeral 51 a denotes a write pixel row. A programming currentis supplied to the source signal line 18 from the source driver IC 14.In FIG. 13 and the like, there is one pixel row into which current iswritten during a period of 1 H, but this is not restrictive. The periodmay be 0.5 H or 2 Hs. Also, although it has been stated that aprogramming current is written into the source signal line 18, thepresent invention is not limited to current programming. The presentinvention may also use voltage programming (FIG. 62, etc.) which writesvoltage into the source signal line 18.

In FIG. 13(a), when the gate signal line 17 a is selected, the currentto be passed through the source signal line 18 is programmed into thetransistor 11 a. At this time, a turn-off voltage is applied to the gatesignal line 17 b, and current does not flow through the EL element 15.This is because when the transistor 11 d is on on the EL element 15, acapacitance component of the EL element 15 is visible from the sourcesignal line 18 and the capacitance prevents sufficient current frombeing programmed into the capacitor 19. Thus, to take the configurationshown in FIG. 1 as an example, the pixel row into which current iswritten is a non-illuminated area 52 as shown in FIG. 13(b).

Suppose an N times larger current is used for programming (it is assumedthat N=10 as described above), the screen becomes 10 times brighter.Thus, 90% of the display screen 50 can be constituted of thenon-illuminated area 52. Thus, for example, if the number of horizontalscanning lines in the screen display area is 220 (S=220) in compliancewith QCIF, 22 horizontal scanning lines can compose a display area 53while 220−22=198 horizontal scanning lines can compose a non-displayarea 52. Generally speaking, if the number of horizontal scanning lines(number of pixel rows) is denoted by S, S/N of the entire areaconstitutes a display area 53, which is illuminated N times morebrightly. Then, the display area 53 is scanned in the vertical directionof the screen. Thus, S(N−1)/N of the entire area is a non-illuminatedarea 52. The non-illuminated area presents a black display (isnon-luminous). Also, the non-luminous area 52 is produced by turning offthe transistor 11 d. Incidentally, although it has been stated that thedisplay area 53 is illuminated N times more brightly, naturally thevalue of N is adjusted by brightness adjustment and gamma adjustment.

In the above example, if a 10 times larger current is used forprogramming, the screen becomes 10 times brighter and 90% of the displayscreen 50 can be constituted of the non-illuminated area 52. However,this does not necessarily mean that R, G, and B pixels constitute thenon-illuminated area 52 in the same proportion. For example, ⅛ of the Rpixels, ⅙ of the G pixels, and 1/10 of the B pixels may constitute thenon-illuminated area 52 with different colors making up differentproportions. It is also possible to allow the non-illuminated area 52(or illuminated area 53) to be adjusted separately among R, G, and B.For that, it is necessary to provide separate gate signal lines 17 b forR, G, and B. However, allowing R, G, and B to be adjusted separatelymakes it possible to adjust white balance, making it easy to adjustcolor balance for each gradation (see FIG. 41).

As shown in FIG. 13(b), pixel rows including the write pixel row 51 acompose a non-illuminated area 52 while an area of S/N (1F/N in thetemporal sense) above the write pixel row 51 a compose a display area 53(when write scans are performed from top to bottom of the screen. Whenthe screen is scanned from bottom to top, the areas change places).Regarding the display condition of the screen, a strip of the displayarea 53 moves from top to bottom of the screen.

In FIG. 13, one display area 53 moves from top to bottom of the screen.At a low frame rate, the movement of the display area 53 is recognizedvisually. It tends to be recognized easily especially when a user closeshis/her eyes or moves his/her head up and down.

To deal with this problem, the display area 53 can be divided into aplurality of parts as shown in FIG. 16. If the total area of the divideddisplay area is S (N−1)/N, the brightness is equal to the brightness inFIG. 13. Incidentally, there is no need to divide the display area 53equally. Also, there is no need to divide the non-display area 52equally.

Dividing the display area 53 reduces flickering of the screen. Thus, aflicker-free good image display can be achieved. Incidentally, thedisplay area 53 may be divided more finely. However, the more finely thedisplay area 53 is divided, the poorer the movie display performancebecomes.

FIG. 17 shows voltage waveforms of gate signal lines 17 and emissionbrightness of the EL element. As can be seen from FIG. 17, a period(1F/N) during which the gate signal line 17 b is set to Vgl is dividedinto a plurality of parts (K parts). That is, a period of 1F/(K·N)during which the gate signal line 17 b is set to Vgl repeats K times.This reduces flickering and implements image display at a low framerate. Preferably, the number of divisions is variable. For example, whenthe user presses a brightness adjustment switch or turns a brightnessadjustment knob, the value of K may be changed in response. Also, theuser may be allowed to adjust brightness. Alternatively, the value of Kmay be changed manually or automatically depending on images or data tobe displayed.

Incidentally, although it has been stated with reference to FIG. 17 andthe like that a period (1F/N) during which the gate signal line 17 b isset to Vgl is divided into a plurality of parts (K parts) and that aperiod of 1F/(K·N) during which the gate signal line 17 b is set to Vglrepeats K times, this is not restrictive. A period of 1F/(K·N) may berepeated L (L≠K) times. In other words, the present invention displaysthe display screen 50 by controlling the period (time) during whichcurrent is passed through the EL element 15. Thus, the idea of repeatingthe 1F/(K·N) period L (L≠K) times is included in the technical idea ofthe present invention. Also, by varying the value of L, the brightnessof the display screen 50 can be changed digitally. For example, there isa 50% change of brightness (contrast) between L=2 and L=3. Also, whendividing the image display area 53, the period when the gate signal line17 b is set to Vgl does not necessarily need to be divided equally.

In the example described above, the display screen 50 is turned on andoff (illuminated and non-illuminated) as the current delivered to the ELelement 15 is switched on and off. That is, approximately equal currentis passed through the transistor 11 a multiple times using electriccharges held in the capacitor 19. The present invention is not limitedto this. For example, the display screen 50 may be turned on and off(illuminated and non-illuminated) by charging and discharging thecapacitor 19.

FIG. 18 shows voltage waveforms applied to gate signal lines 17 toachieve the image display condition shown in FIG. 16. FIG. 18 differsfrom FIG. 15 in the operation of the gate signal line 17 b. The gatesignal line 17 b is turned on and off (Vgl and Vgh) as many times asthere are screen divisions. FIG. 18 is the same as FIG. 15 in otherrespects, and thus description thereof will be omitted.

Since black display on EL display apparatus corresponds to completenon-illumination, contrast does not lower unlike in the case ofintermittent display on liquid crystal display panels. Also, with theconfigurations in FIG. 1, intermittent display can be achieved by simplyturning on and off the transistor 11 d. With the configurations in FIGS.38, and 51, intermittent display can be achieved by simply turning onand off the transistor element 11 e. This is because image data isstored in the capacitor 19 (the number of gradations is infinite becauseanalog values are used). That is, the image data is held in each pixel16 for a period of 1F. Whether to deliver a current which corresponds tothe stored image data to the EL element 15 is controlled by controllingthe transistors 11 d and 11 e.

Thus, the drive method described above is not limited to acurrent-driven type and can be applied to a voltage-driven type as well.That is, in a configuration in which the current passed through the ELelement 15 is stored in each pixel, intermittent driving is implementedby switching on and off the current path between the driver transistor11 and EL element 15.

It is important to maintain terminal voltage of the capacitor 19. Thisis because if the terminal voltage of the capacitor 19 changes(charge/discharge) during one field (frame) period, flickering occurswhen the screen brightness changes and the frame rate lowers. Thecurrent passed through the EL element 15 by the transistor 11 a must behigher than 65%. More specifically, if the initial current written intothe pixel 16 and passed through the EL element 15 is taken as 100%, thecurrent passed through the EL element 15 just before it is written intothe pixel 16 in the next frame (field) must not fall below 65%.

With the pixel configuration shown in FIG. 1, there is no difference inthe number of transistors 11 in a single pixel between when anintermittent display is created and when an intermittent display is notcreated. That is, leaving the pixel configuration as it is, propercurrent programming is achieved by removing the effect of parasiticcapacitance of the source signal line 18. Besides, movie display closeto that of a CRT is achieved.

Also, since the operation clock of the gate driver circuit 12 issignificantly slower than the operation clock of the source drivercircuit 14, there is no need to upgrade the main clock of the circuit.Besides, the value of N can be changed easily.

Incidentally, the image display direction (image writing direction) maybe from top to bottom of the screen in the first field (frame), and frombottom to top of the screen in the second field (frame). That is, anupward direction and downward direction may be repeated alternately.

Alternatively, it is possible to use a downward direction in the firstfield (frame), turn the entire screen into black display (non-display)once, and use an upward direction in the second field (frame). It isalso possible to turn the entire screen into black display (non-display)once.

Incidentally, although top-to-bottom and bottom-to-top writingdirections on the screen are used in the drive method described above,this is not restrictive. It is also possible to fix the writingdirection on the screen to a top-to-bottom direction or bottom-to-topdirection and move the non-display area 52 from top to bottom in thefirst field, and from bottom to top in the second field. Alternatively,it is possible to divide a frame into three fields and assign the firstfield to R, the second field to G, and the third field to B so thatthree fields compose a single frame. It is also possible to display R,G, and B in turns by switching among them every horizontal scanningperiod (1 H) (see FIGS. 175 to 180 and their description). The itemsmentioned above also apply to other examples of the present invention.

The non-display area 52 need not be totally non-illuminated. Weak lightemission or dim image display will not be a problem in practical use. Itshould be regarded to be an area which has a lower display brightnessthan the image display area 53. Also, the non-display area 52 may be anarea which does not display one or two colors out of R, G, and B. Also,it may be an area which displays one or two colors among R, G, and B atlow brightness.

Basically, if the brightness of the display area 53 is kept at apredetermined value, the larger the display area 53, the brighter thedisplay screen 50. For example, when the brightness of the image displayarea 53 is 100 (nt), if the percentage of the display screen 50accounted for by the display area 53 changes from 10% to 20%, thebrightness of the screen is doubled. Thus, by varying the proportion ofthe display area 53 in the entire screen 50, it is possible to vary thedisplay brightness of the screen. The display brightness of the screen50 is proportional to the ratio of the display area 53 to the screen 50.

The size of the display area 53 can be specified freely by controllingdata pulses (ST2) sent to the shift register circuit 61. Also, byvarying the input timing and period of the data pulses, it is possibleto switch between the display condition shown in FIG. 16 and displaycondition shown in FIG. 13. Increasing the number of data pulses in oneIF period makes the screen 50 brighter and decreasing it makes thescreen 50 dimmer. Also, continuous application of the data pulses bringson the display condition shown in FIG. 13 while intermittent applicationof the data pulses brings on the display condition shown in FIG. 16.

FIG. 19(a) shows a brightness adjustment scheme used when the displayarea 53 is continuous as in FIG. 13. The display brightness of thescreen 50 in FIG. 19(a 1) is the brightest, the display brightness ofthe screen 50 in FIG. 19(a 2) is the second brightest, and displaybrightness of the screen 50 in FIG. 19(a 3) is the dimmest. FIG. 19(a)is most suitable for movie display.

Changes from FIG. 19(a 1) to FIG. 19(a 3) (or vice versa) can beachieved easily by controlling the shift register circuit 61 and thelike of the gate driver circuit 12 as described above. In this case,there is no need to vary the Vdd voltage in FIG. 1. That is, thebrightness of the screen 50 can be varied without changing the powersupply voltage. Also, in the process of change from FIG. 19(a 1) to FIG.19(a 3), the gamma characteristics of the screen do not change at all.Thus, the contrast and gradation characteristics of the display screenare maintained regardless of the brightness of the screen 50. This is aneffective feature of the present invention.

In brightness adjustment of a conventional screen, low brightness of thescreen 50 results in poor gradation performance. That is, even if 64gradations can be displayed in a high-brightness display, in most cases,less than half the gradations can be displayed in a low-brightnessdisplay. In contrast, the drive method according to the presentinvention does not depend on the display brightness of the screen andcan display up to 64 gradations, which is the highest.

FIG. 19(b) shows a brightness adjustment scheme used when the displayareas 53 are scattered as in FIG. 16. The display brightness of thescreen 50 in FIG. 19(b 1) is the brightest, the display brightness ofthe screen 50 in FIG. 19(b 2) is the second brightest, and displaybrightness of the screen 50 in FIG. 19(b 3) is the dimmest. Changes fromFIG. 19(b 1) to FIG. 19(b 3) (or vice versa) can be achieved easily bycontrolling the shift register circuit 61 of the gate driver circuit 12and the like as described above. By scattering the display areas 53 asshown in FIG. 19(b), it is possible to eliminate flickering even at alow frame rate.

To eliminate flickering at an even lower frame rate, the display areas53 can be scattered more finely as shown in FIG. 19(c). However, thislowers movie display performance. Thus, the drive method in FIG. 19(a)is suitable for moving pictures. The drive method in FIG. 19(c) issuitable when it is desired to reduce power consumption by displayingstill pictures. Switching from FIG. 19(a) to FIG. 19(c) can be doneeasily by controlling the shift register circuit 61.

Mainly, N=two times, N=4 times, etc. are used in the above example.Needless to say, however, the present invention is not limited tointegral multiples. It is not limited to a value equal to or larger thanN=two, either. For example, less than half the screen 50 may be anon-display area 52 at a certain time point. A predetermined brightnesscan be achieved if a current Iw 5/4 a predetermined value is used forcurrent programming and the EL element is illuminated for 4/5 of 1F.

The present invention is not limited to the above. For example, acurrent Iw 10/4 a predetermined value may be used for currentprogramming to illuminate the EL element for 4/5 of 1F. In this case,the EL element illuminates at twice a predetermined brightness.Alternatively, a current Iw 5/4 a predetermined value may used forcurrent programming to illuminate the EL element for 2/5 of 1F. In thiscase, the EL element illuminates at 1/2 the predetermined brightness.Also, a current Iw 5/4 a predetermined value may be used for currentprogramming to illuminate the EL element for 1/1 of 1F. In this case,the EL element illuminates at 5/4 the predetermined brightness.

Thus, the present invention controls the brightness of the displayscreen by controlling the magnitude of programming current andillumination period IF. Also, by illuminating the EL element for aperiod shorter than the period of 1F, the present invention can insert anon-display area 52, and thereby improve movie display performance. Byilluminating the EL element constantly for the period of 1F, the presentinvention can display a bright screen.

If pixel size is A square mm and predetermined brightness of whiteraster display is B (nt), preferably programming current I (μA)(programming current outputted from the source driver circuit 14) or thecurrent written into the pixel satisfies:(A×B)/20≦I≦(A×B)

This provides good light emission efficiency and solves a shortage ofwrite current.

More preferably, the programming current I (μA) falls within the range:(A×B)/10≦I≦(A×B)

FIG. 20 is an explanatory diagram illustrating another example ofincreasing the current flowing through a source signal line 18. Thismethod selects a plurality of pixel rows simultaneously, charges anddischarges parasitic capacitance and the like of the source signal line18 using the total current flowing through the plurality of pixel rows,and thereby eases a shortage of write current greatly. Since a pluralityof pixel rows are selected simultaneously, drive current per pixel canbe reduced. Thus, it is possible to reduce the current flowing throughthe EL element 15. For ease of explanation, it is assumed that N=10 (thecurrent passed through the source signal line 18 is increased tenfold).

According to the invention described with reference to FIG. 20, M pixelrows are selected simultaneously. A current N times larger than apredetermined current is applied to the source signal line 18 from thesource driver IC 14. A current N/M times larger than the current passedthrough the EL element 15is programmed into each pixel. As an example,to illuminate the EL element 15 at a predetermined emission brightness,current is passed through the EL element 15 for a duration of M/N theduration of one frame (one field) (M/N is used for ease of explanationand is not meant to be restrictive. As described earlier, it can bespecified freely depending on the brightness of the screen 50). Thismakes it possible to charge and discharge parasitic capacitance of thesource signal line 18 sufficiently, resulting in a sufficient resolutionat the predetermined emission brightness.

Current is passed through the EL element 15 only for a period M/N theframe (field) period, but current is not passed during the remainingperiod (1F(N−1)M/N). In this display condition, image data display andblack display (non-illumination) are repeated every 1F. That is, imagedata is displayed at intervals (intermittently) in the temporal sense.This achieves a good display condition without edge blur of images.Also, since the source signal line 18 is driven by an N times largercurrent, it is not affected by parasitic capacitance. Thus, this methodcan accommodate high-resolution display panels.

FIG. 21 is an explanatory diagram illustrating drive waveforms used toimplement the drive method shown in FIG. 20. Waveforms of the turn-offvoltage are denoted by Vgh (H level) while waveforms of the turn-onvoltage are denoted by (L level). The subscripts (such as (1), (2), and(3)) indicate pixel row numbers. Incidentally, the number of rows is 220in the case of a QCIF display panel, and 480 in the case of a VGAdisplay panel.

In FIG. 21, a gate signal line 17 a(1) is selected (Vgl voltage) and aprogramming current flows through the source signal line 18 in thedirection from the transistor 11 a in the selected pixel row to thesource driver circuit 14. For ease of explanation, it is assumed herethat the write pixel row 51 a is the (1)-th pixel row.

The programming current flowing through the source signal line 18 is Ntimes larger than a predetermined value (for ease of explanation, it isassumed that N=10. Of course, since the predetermined value is a datacurrent for use to display images, it is not a fixed value unless in thecase of white raster display). It is also assumed that five pixel rowsare selected simultaneously (M=5). Therefore, ideally the capacitor 19of one pixel is programmed so that a twice (N/M=10/5=2) larger currentwill flow through the transistor 11 a.

When the write pixel row is the (1)-th pixel row, the gate signal lines17 a(1), (2), (3), (4), and (5) are selected as shown in FIG. 21. Thatis, the switching transistors 11 b and the transistors 11 c in the pixelrows (1), (2), (3), (4), and (5) are on. Also, the gate signal lines 17b are 180 degrees out of phase with the gate signal lines 17 a. Thus,the switching transistors 11 d in the pixel rows (1), (2), (3), (4), and(5) are off and current does not flow through the EL elements 15 in thecorresponding pixel rows. That is, the EL elements 15 are innon-illumination mode 52.

Ideally, the transistors 11 a in the five pixels deliver a current ofIw×2 each to the source signal line 18 (i.e., a current ofIw×2×N=Iw×2×5=Iw×10 flows through the source signal line 18. Thus, if apredetermined voltage Iw flows when the N-fold pulse driving accordingto the present invention is not used, a current 10 times larger than Iwflows through the source signal line 18).

Through the above operation (drive method), the capacitor 19 of eachpixel 16 is programmed with a twice larger current. For ease ofunderstanding, it is assumed here that the transistors 11 a have equalcharacteristics (Vt and S value)

Since five pixel rows are selected simultaneously (M=5), five drivertransistors 11 a operate. That is, 10/5=2 times larger current flowsthrough the transistor 11 a per pixel. The total programming current ofthe five transistors 11 a flows through the source signal line 18. Forexample, if a current conventionally written into the write pixel row 51a is Iw, a current of Iw×10 is passed through the source signal line 18.The write pixel rows 51 b into which image data is written later thanthe write pixel row (1) are auxiliary pixel rows used to increase theamount of current delivered to the source signal line 18. However, thereis no problem because regular image data is written into the write pixelrows 51 b later.

Thus, the four pixel rows 51 b provide the same display as the pixel row51 a during a period of 1 H. Consequently, at least the write pixel row51 a and the pixel rows 51 b selected to increase current are innon-display mode 52. However, in the pixel configuration of a currentmirror, such as shown in FIG. 38, or pixel configuration for voltageprogramming, the pixel rows may be in display mode.

After 1 H, the gate signal line 17 a(1) becomes deselected and a turn-onvoltage (Vgl) is applied to the gate signal line 17 b. At the same time,the gate signal line 17 a(6) is selected (Vgl voltage) and a programmingcurrent flows through the source signal line 18 in the direction fromthe transistor 11 a in the selected pixel row (6) to the source drivercircuit 14. Through this operation, regular image data is held in thepixel row (1).

After the next 1 H, the gate signal line 17 a(2) becomes deselected anda turn-on voltage (Vgl) is applied to the gate signal line 17 b. At thesame time, the gate signal line 17 a(7) is selected (Vgl voltage) and aprogramming current flows through the source signal line 18 in thedirection from the transistor 11 a in the selected pixel row (7) to thesource driver circuit 14. Through this operation, regular image data isheld in the pixel row (2). The entire screen is redrawn as it is scannedby shifting pixel rows one by one through the above operations.

With the drive method in FIG. 20, since each pixel is programmed with atwice larger current, ideally the emission brightness of the EL element15 of each pixel is two times higher. Thus, the brightness of thedisplay screen is twice higher than a predetermined value. To equalizethis brightness with the predetermined brightness, an area whichincludes the write pixel rows 51 and which is half as large as thedisplay screen 50 can be turned into a non-display area 52 asillustrated in FIG. 16.

As is the case with FIG. 13, when one display area 53 moves from top tobottom of the screen as shown in FIG. 20, the movement of the displayarea 53 is recognized visually if a low frame rate is used. It tends tobe recognized easily especially when the user closes his/her eyes ormoves his/her head up and down.

To deal with this problem, the display area 53 can be divided into aplurality of parts as illustrated in FIG. 22. If the total area of thedivided non-display area 52 is S (N−1)/N, the brightness is equal to thebrightness of the undivided display area.

FIG. 23 shows voltage waveforms applied to gate signal lines 17. FIG. 21differs from FIG. 23 basically in the operation of the gate signal line17 b. The gate signal line 17 b is turned on and off (Vgl and Vgh) asmany times as there are screen divisions. FIG. 23 is the same as FIG. 21in other respects, and thus description thereof will be omitted.

As described above, dividing the display area 53 reduces flickering ofthe screen. Thus, a flicker-free good image display can be achieved.Incidentally, the display area 53 may be divided more finely. The morefinely the display area 53 is divided, the less flickering occurs. Sincethe EL element 15 is highly responsive, even if it is turned on and offat intervals shorter than 5 μsec, there is no lowering of the displaybrightness.

With the drive method according to the present invention, the EL element15 can be turned on and off by turning on and off a signal applied tothe gate signal line 17 b. Thus, the drive method according to thepresent invention can perform control using a low frequency on the orderof KHz. Also, it does not need an image memory or the like in order toinsert a black screen (insert anon-display area 52). Thus, the drivecircuit or method according to the present invention can be implementedat low costs.

FIG. 24 shows a case in which two pixel rows are selectedsimultaneously. It was found that on a display panel formed bylow-temperature polysilicon technology, a method in which two pixel rowswere selected simultaneously provided uniform display on a practicallevel. Probably this is because driver transistors 11 a in adjacentpixels had very similar characteristics. In laser annealing, goodresults were obtained when laser stripes were irradiated in parallelwith the source signal line 18.

This is because that part of a semiconductor film which is annealedsimultaneously has uniform characteristics. That is, the semiconductorfilm is created uniformly within an irradiation range of laser stripesand the Vt and mobility of the transistors which use the semiconductorfilm are almost uniform. Thus, if a striped laser shot is moved inparallel with the source signal line 18, pixels (a pixel column, i.e.,pixels arranged vertically on the screen) along the source signal line18 take on almost equal characteristics. Therefore, if a plurality ofpixel rows are turned on simultaneously for current programming, thecurrent obtained by dividing the programming current by the number ofselected pixels are programmed almost uniformly into the pixels Thismakes it possible to program a current close to a target value andachieve uniform display. Thus, the direction of a laser shot and thedrive method described with reference to FIG. 24 and the like have asynergistic effect.

As described above, if the direction of a laser shot is made to coincideapproximately with the direction of the source signal line 18 (see FIG.7), the characteristics of the pixel transistors 11 a arrangedvertically become almost uniform, making it possible to do propercurrent programming (even if the characteristics of the pixeltransistors 11 a arranged horizontally are not uniform). The aboveoperation is performed in sync with 1 H (one horizontal scanning period)by shifting selected pixel rows one by one or by shifting two or moreselected pixel rows at once.

Incidentally, as described with reference to FIG. 8, the direction ofthe laser shot does not always need to be parallel with the direction ofthe source signal line 18. This is because even if the laser shot isdirected at angles to the source signal line 18, pixel transistors 11 aplaced along one source signal line 18 can be made to take on almostequal characteristics. Thus, directing a laser shot in parallel with thesource signal line 18 means bringing a pixel vertically adjacent to anarbitrary pixel along the source signal line 18 into a laser irradiationrange. Besides, a source signal line 18 generally constitutes wiringwhich transmits programming current or voltage used as a video signal.

Incidentally, in the examples of the present invention a write pixel rowis shifted every 1 H, but this is not restrictive. Pixel rows may beshifted every 2 Hs (two pixel rows at a time). Also, more than two pixelrows may be shifted at a time. Also, pixel rows may be shifted atdesired time intervals or every second pixel may be shifted.

The shifting interval may be varied according to locations on thescreen. For example, the shifting interval may be decreased in themiddle of the screen, and increased at the top and bottom of the screen.For example, a pixel row may be shifted at intervals of 200 μsec. in themiddle of the screen 50, and at intervals of 100 μsec. at the top andbottom of the screen 50. This increases emission brightness in themiddle of the screen 50 and decreases it around the perimeters (at thetop and bottom of the screen 50)). Needless to say, the shiftinginterval is varied smoothly among the top, middle, and bottom of thescreen 50 to avoid brightness contours.

Incidentally, the reference voltage of the source driver circuit 14 maybe varied with the scanning location on the screen 50 (see FIG. 146,etc.). For example, a reference current of 10 μA is used in the middleof the screen 50 and a reference current of 5 μA is used at the top ofthe screen 50. Varying a reference current in this way corresponding toa location in the screen 50, increases emission brightness in the middleof the screen 50 and decreases it around the perimeters (at the top andbottom of the screen 50)). Needless to say, the reference current isvaried smoothly among the top, middle, and bottom of the screen 50 toavoid brightness contours.

Also, it goes without saying that images may be displayed by combining adrive method which varies the pixel-row shifting interval with thelocation on the screen and a drive method which varies the referencevoltage with the location on the screen 50.

The shifting interval may be varied on a frame-by-frame basis. Also, itis not strictly necessary to select consecutive pixel rows. For example,every second pixel row may be selected.

Specifically, a possible drive method involves selecting the first andthird pixel rows in the first horizontal scanning period, the second andfourth pixel rows in the second horizontal scanning period, the thirdand fifth pixel rows in the third horizontal scanning period, and thefourth and sixth pixel rows in the fourth horizontal scanning period. Ofcourse, a drive method which involves selecting the first, third, andfifth pixel rows in the first horizontal scanning period also belongs tothe technical category of the present invention. Also, one in every fewpixel rows maybe selected.

Incidentally, the combination of the direction of a laser shot andselection of multiple pixel rows is not limited to the pixelconfigurations in FIGS. 1, 2, and 32, but it is also applicable to othercurrent-driven pixel configurations such as the current-mirror pixelconfigurations in FIGS. 38, 42, 50, etc. Also, it can be applied tovoltage-driven pixel configurations in FIGS. 43, 51, 54, 62, etc. Thisis because as long as transistors in upper and lower parts of the pixelhave equal characteristics, current programming can be performedproperly using the voltage value applied to the same source signal line18.

In FIG. 24, when the write pixel row is the (1)-th pixel row, the gatesignal lines 17 a(1) and (2) are selected (see FIG. 25). That is, theswitching transistors 11 b and the transistors 11 c in the pixel rows(1) and (2) are on. Thus, at least the switching transistors 11 d in thepixel rows (1) and (2) are off and current does not flow through the ELelements 15 in the corresponding pixel rows. That is, the EL elements 15are in non-illumination mode 52. Incidentally, in FIG. 24, the displayarea 53 is divided into five parts to reduce flickering.

Ideally, the transistors 11 a in the two pixel rows deliver a current ofIw×5 each to the source signal line 18 (when N=10. Since K=2, a currentof Iw×K×5=Iw×10 flows through the source signal line 18). Then, thecapacitor 19 of each pixel 16 is programmed with a 5 times largercurrent.

Since two pixel rows are selected simultaneously (K=2), two drivertransistors 11 a operate. That is, 10/2=5 times larger current flowsthrough the transistor 11 a per pixel. The total programming current ofthe two transistors 11 a flows through the source signal line 18.

For example, if the current written into the write pixel row 51 a is Id,a current of Iw×10 is passed through the source signal line 18. There isno problem because regular image data is written into the write pixelrow 51 b later. The pixel row 51 b provides the same display as thepixel row 51 a during a period of 1 H. Consequently, at least the writepixel row 51 a and the pixel row 51 b selected to increase current arein non-display mode 52.

After the next 1 H, the gate signal line 17 a(1) becomes deselected anda turn-on voltage (Vgl) is applied to the gate signal line 17 b. At thesame time, the gate signal line 17 a(3) is selected (Vgl voltage) and aprogramming current flows through the source signal line 18 in thedirection from the transistor 11 a in the selected pixel row (3) to thesource driver circuit 14. Through this operation, regular image data isheld in the pixel row (1).

After the next 1 H, the gate signal line 17 a(2) becomes deselected anda turn-on voltage (Vgl) is applied to the gate signal line 17 b. At thesame time, the gate signal line 17 a(4) is selected (Vgl voltage) and aprogramming current flows through the source signal line 18 in thedirection from the transistor 11 a in the selected pixel row (4) to thesource driver circuit 14. Through this operation, regular image data isheld in the pixel row (2). The entire screen is redrawn as it is scannedby shifting pixel rows one by one through the above operations (ofcourse, two or more pixel rows may be shifted simultaneously. Forexample, in the case of pseudo-interlaced driving, two pixel rows willbe shifted at a time. Also, from the viewpoint of image display, thesame image may be written into two or more pixel rows).

As in the case of FIG. 16, with the drive method in FIG. 24, since eachpixel is programmed with a five times larger current (voltage), ideallythe emission brightness of the EL element 15 is five times higher. Thus,the brightness of the display area 53 is five times higher than apredetermined value. To equalize this brightness with the predeterminedbrightness, an area which includes the write pixel rows 51 and which is1/5 the display screen 50 can be turned into a non-display area 52.

As shown in FIG. 27, two write pixel rows 51 (51 a and 51 b) areselected in sequence from the upper side to the lower side of the screen50 (see also FIG. 26. Pixels 16 a and 16 b are selected in FIG. 26).However, at the bottom of the screen, there does not exist 51 b althoughthe write pixel row 51 a exists as shown in FIG. 27(b). That is, thereis only one pixel row to be selected. Thus, the current applied to thesource signal line 18 is all written into the write pixel row 51 a.Consequently, twice as large a current as usual is written into thewrite pixel row 51 a.

To deal with this problem, the present invention forms (places) a dummypixel row 281 at the bottom of the screen 50, as shown in FIG. 27(b).Thus, after the pixel row at the bottom of the screen 50 is selected,the final pixel row of the screen 50 and the dummy pixel row 281 areselected. Consequently, a prescribed current is written into the writepixel row in FIG. 27(b).

Incidentally, although the dummy pixel row 281 is illustrated as beingadjacent to the top end or bottom end of the display screen 50, this isnot restrictive. It may be formed at a location away from the displayscreen 50. Besides, the dummy pixel row 281 does not need to contain aswitching transistor 11 d or EL element 15 such as those shown inFIG. 1. This reduces the size of the dummy pixel row 281.

FIG. 28 shows a mechanism of how the state shown in FIG. 27(b) takesplace. As can be seen from FIG. 28, after the pixel 16 c at the bottomof the screen 50 is selected, the final pixel row (dummy pixel row) 281of the screen 50 is selected. The dummy pixel row 281 is placed outsidethe screen 50. That is, the dummy pixel row (dummy pixel) 281 does notilluminate, is not illuminated, or is hidden even if illuminated. Forexample, contact holes between the pixel electrode 105 and transistor 11are eliminated, no EL film is formed on the dummy pixel row 281, or thelike. Also, an insulating film may be formed on the pixel electrode 105of the dummy pixel row 271.

Although it has been stated with reference to FIG. 27 that the dummypixel (row) 281 is provided (formed or placed) at the bottom of thescreen 50, this is not restrictive. For example when the screen isscanned from bottom to top (inverse scanning) as shown in FIG. 29(a), adummy pixel row 281 should also be formed at the top of the screen 50 asshown in FIG. 29(b). That is, dummy pixel rows 281 are formed (placed)both at the top and bottom of the screen 50. This configurationaccommodates inverse scanning of the screen as well. Two pixel rows areselected simultaneously in the example described above.

The present invention is not limited to this. For example, five pixelrows may be selected simultaneously (see FIG. 23). When five pixel rowsare selected simultaneously, four dummy pixel rows 281 should be formed.That is, the number of dummy pixel rows 281 equals the number of pixelrows selected simultaneously minus one. However, this is true only whenthe selected pixel rows are shifted one by one. When two or more pixelrows are shifted at a time, (M−1)×L dummy pixel rows should be formed,where M is the number of pixels selected and L is the number of pixelrows shifted at a time.

The dummy pixel row configuration or dummy pixel row driving accordingto the present invention uses one or more dummy pixel rows. Of course,it is preferable to use the dummy pixel row driving and N-fold pulsedriving in combination.

In the drive method which selects two or more pixel rows at a time, thelarger the number of pixel rows selected simultaneously, the moredifficult it becomes to absorb variations in the characteristics of thetransistors 11 a. However, the current programmed into one pixelincreases with decreases in the number M of pixel rows selectedsimultaneously, resulting in a large current flowing through the ELelement 15, which in turn makes the EL element 15 prone to degradation.

FIG. 30 shows how to solve this problem. The basic concept behind FIG.30 is to use a method of selecting a plurality of pixel rowssimultaneously during ½ H (½ of a horizontal scanning period) asdescribed with reference to FIGS. 22 and 29 and to use a method ofselecting one pixel row in the latter ½ H (½ of the horizontal scanningperiod) as described with reference to FIGS. 5 and 13. This combinationmakes it possible to absorb variations in the characteristics of thetransistors 11 a and achieve high speed and uniform surfaces.Incidentally, although the period of ½H is used for ease ofunderstanding, this is not restrictive. The first period may be ¼ H andthe second period may be ¾ H.

Referring to FIG. 30, for ease of understanding, it is assumed that fivepixel rows are selected simultaneously in the first period and that onepixel row is selected in the second period. First, as shown in FIG. 30(a1), in the first period (first ½ H), five pixel rows are selectedsimultaneously. This operation has been described with reference to FIG.22, and thus description thereof will be omitted. As an example, it isassumed that the current passed through the source signal line 18 is 25times as large as a predetermined value. Thus, the transistor 11 a inthe pixel 16 (in the pixel configuration in FIG. 1) is programmed with afive times larger current (25/5 pixel rows=5). Since the current is 25times larger, the parasitic capacitance generated in the source signalline 18 and the like is charged and discharged in an extremely shortperiod. Consequently, the potential of the source signal line 18 reachesa target potential in a short period of time and the terminal voltage ofthe capacitor 19 of each pixel 16 is programmed to pass a 25 timeslarger current. The 25 times larger current is applied in the first ½ H(½ of the horizontal scanning period).

Naturally, since the same image data is written into the five writepixel rows, the transistors 11 d in the five write pixel rows are turnedoff in order not to display the image. Thus, the display condition is asshown in FIG. 30(a 2).

In the next ½ H period, one pixel is selected for current (voltage)programming. The condition is as shown in FIG. 30(b 1). Current(voltage) programming is performed so as to pass a five times largercurrent through the write pixel row 51 a as in the first period. Equalcurrent is passed in FIG. 30(a 1) and FIG. 30(b 1) to reach a targetcurrent more quickly by decreasing the changes in the terminal voltageof the programmed capacitor 19.

Specifically, in FIG. 30(a 1), current is passed through a plurality ofpixels, approaching an approximate target value quickly. In this firststage, since a plurality of transistors 11 a are programmed, variationsin the transistors cause error with respect to the target value. In thesecond stage, only a pixel row where data will be written and held isselected and complete programming is performed by changing the value ofcurrent from the approximate target value to a predetermined targetvalue.

Incidentally, scanning of the non-illuminated area 52 from top to bottomof the screen and scanning of the write pixel rows 51 a from top tobottom of the screen are performed in the same manner as in examples inFIG. 13 and the like, and thus description thereof will be omitted.

FIG. 31 shows drive waveforms used to implement the drive method shownin FIG. 30. As can be seen from FIG. 31, 1 H (one horizontal scanningperiod) consists of two phases. An ISEL signal is used to switch betweenthe two phases. The ISEL signal is illustrated in FIG. 31.

First, the ISEL signal will be described. The driver circuit 14 whichperforms operations shown in FIG. 30 comprises a current output circuitA and current output circuit B. Each of the current output circuitsconsists of a D/A circuit which converts 8-bit gradation data fromdigital to analog, an operation amplifier, etc. In the example in FIG.30, the current output circuit A is configured to output 25 times largercurrent. On the other hand, the current output circuit B is configuredto output 5 times larger current. Outputs from the current outputcircuit A and current output circuit B are controlled by a switchcircuit formed (placed) in a current output section through the ISELsignals and are applied to the source signal line 18. Such currentoutput circuits are placed on each source signal line 18.

When the ISEL signal is low, the current output circuit A which outputs25 times larger current is selected and current from the source signalline 18 is absorbed by the source driver IC 14 (more precisely, thecurrent is absorbed by the current output circuit A formed in the sourcedriver IC 14). The magnification (such as ×25 or ×5) of the current fromthe current output circuits can be adjusted easily using a plurality ofresisters and an analog switch.

As shown in FIG. 30, when the write pixel row is the (1)-th pixel row(see the 1H column in FIG. 30), the gate signal lines 17 a(1), (2), (3),(4), and (5) are selected (in the case of configuration shown in FIG.1). That is, the switching transistors 11 b and the transistors 11 c inthe pixel rows (1), (2), (3), (4), and (5) are on. Besides, since ISELis low, the current output circuit A which outputs 25 times largercurrent is selected and connected to the source signal line 18. Also, aturn-off voltage (Vgh) is applied to the gate signal line 17 b. Thus,the switching transistors 11 d in the pixel rows (1), (2), (3), (4), and(5) are off and current does not flow through the EL elements 15 in thecorresponding pixel rows. That is, the EL elements 15 are innon-illumination mode 52.

Ideally, the transistors 11 a in the five pixels deliver a current ofIw×2 each to the source signal line 18. Then, the capacitor 19 of eachpixel 16 is programmed with a five times larger current. For ease ofunderstanding, it is assumed here that the transistors have equalcharacteristics (Vt and S value).

Since five pixel rows are selected simultaneously (K=5), five drivertransistors 11 a operate. That is, 25/5=5 times larger current flowsthrough the transistor 11 a per pixel. The total programming current ofthe five transistors 11 a flows through the source signal line 18. Forexample, if the current written into the write pixel row 51 a by aconventional drive method is Iw, a current of Iw×25 is passed throughthe source signal line 18. The write pixel rows 51 b into which imagedata is written later than the write pixel row (1) are auxiliary pixelrows used to increase the amount of current delivered to the sourcesignal line 18. However, there is no problem because regular image datais written into the write pixel rows 51 b later.

Thus, the pixel rows 51 b provide the same display as the pixel row 51 aduring a period of 1 H. Consequently, at least the write pixel row 51 aand the pixel rows 51 b selected to increase current are in non-displaymode 52.

In the next ½ H period (½ of the horizontal scanning period), only thewrite pixel row 51 a is selected. That is, only the (1)-th pixel row isselected. As can be seen from FIG. 31, a turn-on voltage (Vgl) isapplied only to the gate signal line 17 a(1) and a turn-off voltage(Vgh) is applied to the gate signal lines 17 a(2), (3), (4), and (5).Thus, the transistor 11 a in the pixel row (1) is in operation(supplying current to the source signal line 18), but the switchingtransistors 11 b and the transistors 11 c in the pixel rows (2), (3),(4), and (5) are off. That is, they are non-selected.

Besides, since ISEL is high, the current output circuit B which outputs5 times larger current is selected and connected to the source signalline 18. Also, a turn-off voltage (Vgh) is applied to the gate signalline 17 b, which is in the same state as during the first ½ H. Thus, theswitching transistors 11 d in the pixel rows (1), (2), (3), (4), and (5)are off and current does not flow through the EL elements 15 in thecorresponding pixel rows. That is, the EL elements 15 are innon-illumination mode 52.

Thus, each transistor 11 a in the pixel row (1) deliver a current ofIw×5 to the source signal line 18. Then, the capacitor 19 in each pixelrow (1) is programmed with a 5 times larger current.

In the next horizontal scanning period, the write pixel row shifts byone. That is, the pixel row (2) becomes the current write pixel row.During the first ½ H period, when the write pixel row is the (2)-thpixel row, the gate signal lines 17 a(2), (3), (4), and (5) and (6) areselected. That is, the switching transistors 11 b and the transistors 11c in the pixel rows (2), (3), (4), (5), and (6) are on. Besides, sinceISEL is low, the current output circuit A which outputs 25 times largercurrent is selected and connected to the source signal line 18. Also, aturn-off voltage (Vgh) is applied to the gate signal line 17 b.

Thus, the switching transistors 11 d in the pixel rows (2), (3), (4),(5), and (6) are off and current does not flow through the EL elements15 in the corresponding pixel rows. That is, the EL elements 15 are innon-illumination mode 52. On the other hand, since Vgl voltage isapplied to the gate signal line 17 b(1) of the pixel row (1), thetransistor 11 d is on and the EL element 15 in the pixel row (1)illuminates.

Since five pixel rows are selected simultaneously (K=5), five drivertransistors 11 a operate. That is, 25/5=5 times larger current flowsthrough the transistor 11 a per pixel. The total programming current ofthe five transistors 11 a flows through the source signal line 18.

In the next ½ H period (½ of the horizontal scanning period), only thewrite pixel row 51 a is selected. That is, only the (2)-th pixel row isselected. As can be seen from FIG. 31, a turn-on voltage (Vgl) isapplied only to the gate signal line 17 a(2) and a turn-off voltage(Vgh) is applied to the gate signal lines 17 a(3), (4), (5), and (6).

Thus, the transistors 11 a in the pixel rows (1) and (2) are inoperation (the pixel row (1) supplies current to the EL element 15 andthe pixel row (2) supplies current to the source signal line 18), butthe switching transistors 11 b and the transistors 11 c in the pixelrows (3), (4), (5), and (6) are off. That is, they are non-selected.

Besides, since ISEL is high, the current output circuit B which outputs5 times larger current is selected and the current output circuit 1222 bis connected to the source signal line 18. Also, a turn-off voltage(Vgh) is applied to the gate signal line 17 b, which is in the samestate as during the first ½ H. Thus, the switching transistors 11 d inthe pixel rows (2), (3), (4), (5), and (6) are off and current does notflow through the EL elements 15 in the corresponding pixel rows. Thatis, the EL elements 15 are in non-illumination mode 52.

Thus, each transistor 11 a in the pixel row (1) deliver a current ofIw×5 to the source signal line 18. Then, the capacitor 19 in each pixelrow (1) is programmed with a 5 times larger current. The entire screenis drawn as the above operations are performed in sequence.

The drive method described with reference to FIG. 30 selects G pixelrows (G is 2 or larger) in the first period and does programming in sucha way as to pass N times larger current through each pixel row. In thesecond period, the drive method selects B pixel rows (B is smaller thanG, but not smaller than 1) and does programming in such a way as to passan N times larger current through the pixels.

Another scheme is also available. It selects G pixel rows (G is 2 orlarger) in the first period and does programming in such a way that thetotal current in all the pixel rows will be an N times larger current.In the second period, this scheme selects B pixel rows (B is smallerthan G, but not smaller than 1) and does programming in such a way thatthe total current in the selected pixel rows (the current in the onepixel row if one pixel row is selected) will be an N times largercurrent. For example, in FIG. 30(a 1), five pixel rows are selectedsimultaneously and a twice larger current is passed through thetransistor 11 a in each pixel. Thus, 5×2=10 times larger current flowsthrough the source signal line 18. In the second period, one pixel rowis selected in FIG. 30(b 1) A 10 times larger current is passed throughthe transistor 11 a in this pixel.

Incidentally, although a plurality of pixel rows are selectedsimultaneously in a period of ½ H and a single pixel row is selected ina period of ½ H in FIG. 31, this is not restrictive. A plurality ofpixel rows may be selected simultaneously in a period of ¼ H and asingle pixel row may be selected in a period of ¾ H. Also, the sum ofthe period in which a plurality of pixel rows are selectedsimultaneously and the period in which a single pixel row is selected isnot limited to 1 H. For example, the total period may be 2 Hs or 1.5 Hs.

In FIG. 30, it is also possible to select two pixel rows simultaneouslyin the second period after selecting five pixel rows simultaneously inthe first ½ H. This can also achieve a practically acceptable imagedisplay.

In FIG. 30, pixel rows are selected in two stages—five pixel rows areselected simultaneously in the first ½ H period and a single pixel rowis selected in the second ½ H period, but this is not restrictive. Forexample, it is also possible to select five pixel rows simultaneously inthe first stage, select two of the five pixel rows in the second stage,and finally select one pixel row in the third stage. In short, imagedata may be written into pixel rows in two or more stages.

In the example described above, pixel rows are selected one by one andprogrammed with current, or two or more pixel rows are selected at atime and programmed with current. However, the present invention is notlimited to this. It is also possible to use a combination of the twomethods according to image data: the method of selecting pixel rows oneby one and programming them with current and the method of selecting twoor more pixel rows at a time and programming them with current.

FIG. 186 combines a drive system which selects pixel rows one by one anda drive method which selects multiple pixel rows one by one.

In the case where multiple pixel rows are selected at a time, it isassumed for ease of understanding that two pixel rows are selectedsimultaneously as illustrated in FIG. 186(a 2) Thus, one dummy pixel row281 each is formed at the top and bottom of the screen.

The drive system which selects pixel rows one by one does not need touse dummy pixel rows.

Incidentally, for ease of understanding, it is assumed that the sourcedriver IC 14 in FIG. 186(a 1) (one pixel row is selected) and FIG. 186(a2) (two pixel rows are selected) output equal currents.

Thus, the drive system which selects two pixel rows at a time as shownin FIG. 186(a 2) provides half the screen brightness compared to thedrive system which selects pixel rows one by one as shown in FIG. 186(a1).

To provide equal screen brightness, the duty ratio in FIG. 186(a 2) canbe doubled (e.g., if the duty ratio in FIG. 186(a 1) is ½, the dutyratio in FIG. 186(a 2) can be set to 1/1=1/2×2).

Also, the magnitude of the reference current inputted in the sourcedriver IC 14 can be varied twice as much. Alternatively, the programmingcurrent can be doubled.

FIG. 186(a 1) shows a typical drive method according to the presentinvention.

If input video signals are non-interlaced (progressive) signals, thedrive system in FIG. 186(a 1) is used.

If input video signals are interlaced signals, the drive system in FIG.186(a 2) is used.

Also, if video signals have low image resolution, the drive system inFIG. 186(a 2) is used.

It is also possible to use the drive method in FIG. 186(a 2) for movingpictures and the drive method in FIG. 186(a 1) for still pictures.

The drive method in FIG. 186(a 1) and drive method in FIG. 186(a 2) canbe switched easily by controlling the start pulse supplied to the gatedriver circuit 12.

A problem is that the drive system which selects two pixel rows at atime as shown in FIG. 186(a 2) provides half the screen brightnesscompared to the drive system which selects pixel rows one by one (FIG.186(a 1)).

To provide equal screen brightness, the duty ratio in FIG. 186(a 2) canbe doubled (e.g., if the duty ratio in FIG. 186(a 1) is 1/2, the dutyratio in FIG. 186(a 2) can be set to 1/1=1/2×2).

That is, the proportions of the non-display area 52 and display area 53in FIG. 186(b) can be varied.

The proportions of the non-display area 52 and display area 53 in FIG.186(b) can be varied easily by controlling the start pulse supplied tothe gate driver circuit 12. That is, the drive mode in FIG. 186(b) canbe varied according the display mode in FIGS. 186(a 1) and 186(a 2).

Now, interlaced driving according to the present invention will bedescribed below in more detail. FIG. 187 shows a configuration of thedisplay panel according to the present invention which performs theinterlaced driving. In FIG. 187, the gate signal lines 17 a ofodd-numbered pixel rows are connected to a gate driver circuit 12 a 1.The gate signal lines 17 a of even-numbered pixel rows are connected toa gate driver circuit 12 a 2. On the other hand, the gate signal lines17 b of the odd-numbered pixel rows are connected to a gate drivercircuit 12 b 1. The gate signal lines 17 b of the even-numbered pixelrows are connected to a gate driver circuit 12 b 2.

Thus, through operation (control) of the gate driver circuit 12 a 1,image data in the odd-numbered pixel rows are rewritten in sequence. Inthe odd-numbered pixel rows, illumination and non-illumination of the ELelements are controlled through operation (control) of the gate drivercircuit 12 b 1. Also, through operation (control) of the gate drivercircuit 12 a 2, image data in the even-numbered pixel rows are rewrittenin sequence. In the even-numbered pixel rows, illumination andnon-illumination of the EL elements are controlled through operation(control) of the gate driver circuit 12 b 2.

FIG. 188(a) shows operating state in the first field of the displaypanel. FIG. 188(b) shows operating state in the second field of thedisplay panel. In FIG. 188, the oblique hatching which marks the gatedriver circuits 12 indicates that the gate driver circuits 12 are nottaking part in data scanning operation. Specifically, in the first fieldin FIG. 188(a), the gate driver circuit 12 a 1 is operating for writecontrol of programming current and the gate driver circuit 12 b 2 isoperating for illumination control of the EL element 15. In the secondfield in FIG. 188(b), the gate driver circuit 12 a 2 is operating forwrite control of programming current and the gate driver circuit 12 b 1is operating for illumination control of the EL element 15. The aboveoperations are repeated within the frame.

FIG. 189 shows image display status in the first field. FIG. 189(a)illustrates write pixel rows (locations of odd-numbered pixel rowsprogrammed with current (voltage). The location of the write pixel rowis shifted in sequence: FIG. 189(a 1)→(a 2)→(a 3). In the first field,odd-numbered pixel rows are rewritten in sequence (image data in theeven-numbered pixel rows are maintained). FIG. 189(b) illustratesdisplay status of odd-numbered pixel rows. Incidentally, FIG. 189(b)illustrates only odd-numbered pixel rows. Even-numbered pixel rows areillustrated in FIG. 189(c). As can be seen from FIG. 189(b), the ELelements 15 of the pixels in the odd-numbered pixel rows arenon-illuminated. On the other hand, the even-numbered pixel rows arescanned in both display area 53 and non-display area 52 as shown in FIG.189(c) (N-fold pulse driving).

FIG. 190 shows image display status in the second field. FIG. 190(a)illustrates write pixel rows (locations of odd-numbered pixel rowsprogrammed with current (voltage). The location of the write pixel rowis shifted in sequence: FIG. 190(a 1)→(a 2)→(a 3). In the second field,even-numbered pixel rows are rewritten in sequence (image data in theodd-numbered pixel rows are maintained). FIG. 190(b) illustrates displaystatus of odd-numbered pixel rows. Incidentally, FIG. 190(b) illustratesonly odd-numbered pixel rows. Even-numbered pixel rows are illustratedin FIG. 190(c). As can be seen from FIG. 190(b), the EL elements 15 ofthe pixels in the even-numbered pixel rows are non-illuminated. On theother hand, the odd-numbered pixel rows are scanned in both display area53 and non-display area 52 as shown in FIG. 190(c) (N-fold pulsedriving).

In this way, interlaced driving can be implemented easily on an ELdisplay panel. Also, N-fold pulse driving eliminates shortages of writecurrent and blurred moving pictures. Besides, current (voltage)programming and illumination of EL elements 15 can be controlled easilyand circuits can be implemented easily.

Incidentally, the drive method according to the present invention is notlimited to those shown in FIGS. 189 and 190. For example, a drive methodshown in FIG. 191 is also available. Whereas in FIGS. 189 and 190, theodd-numbered pixel rows or even-numbered pixel rows being programmedbelong to a non-display area 52 (non-illumination or black display), theexample in FIG. 191 involves synchronizing the gate driver circuits 12 b1 and 12 b 2 which control illumination of the EL elements 15. Needlessto say, however, the write pixel row 51 being programmed with current(voltage) belongs to a non-display area (there is no need for this inthe case of the current-mirror pixel configuration in FIG. 38). In FIG.191, since illumination control is common to the odd-numbered pixel rowsand even-numbered pixel rows, there is no need to provide two gatedriver circuits: 12 b 1 and 12 b 2. The gate driver circuit 12 b alonecan perform illumination control.

The drive method in FIG. 191 uses illumination control for bothodd-numbered pixel rows and even-numbered pixel rows. However, thepresent invention is not limited to this. FIG. 192 shows an example inwhich illumination control varies between odd-numbered pixel rows andeven-numbered pixel rows. In FIG. 192, the illumination mode (displayarea 53 and non-display area 52) of odd-numbered pixel rows andillumination mode of even-numbered pixel rows have opposite patterns.Thus, display area 53 and non-display area 52 have the same size.However, this is not restrictive.

In the above example, the drive method programs pixel rows with current(voltage) one at a time. However, the drive method according to thepresent invention is not limited to this. Needless to say, two pixelrows (a plurality of pixel rows) maybe programmed with current (voltage)simultaneously as shown in FIG. 193.

Besides, in FIGS. 190 and 189, it is not strictly necessary to put allthe odd-numbered pixel rows or even-numbered pixel rows innon-illumination mode.

The N-fold pulse driving method according to the present invention usesthe same waveform for the gate signal lines 17 b of different pixel rowsand applies current by shifting the pixel rows at 1 H intervals. The useof such scanning makes it possible to shift illuminating pixel rows insequence with the illumination duration of the EL elements 15 fixed to1F/N. It is easy to shift pixel rows in this way while using the samewaveform for the gate signal lines 17 b of the pixel rows. It can bedone by simply controlling data ST1 and ST2 applied to the shiftregister circuits 61 a and 61 b in FIG. 6. For example, if Vgl is outputto the gate signal line 17 b when input ST1 is low and Vgh is output tothe gate signal line 17 b when input ST1 is high, ST2 applied to theshift register circuit 17 b can be set low for a period of 1F/N and sethigh for the remaining period. Then, inputted ST2 can be shifted using aclock CLK2 synchronized with 1 H.

Incidentally, the EL elements 15 must be turned on and off at intervalsof 0.5 msec or longer. Short intervals will lead to insufficient blackdisplay due to persistence of vision, resulting in blurred images andmaking it look as if the resolution has lowered. This also represents adisplay state of a data holding display. However, increasing the on/offintervals to 100 msec will cause flickering. Thus, the on/off intervalsof the EL elements must be not shorter than 0.5 μsec and not longer than100 msec. More preferably, the on/off intervals should be from 2 msec to30 msec (both inclusive). Even more preferably, the on/off intervalsshould be from 3 msec to 20 msec (both inclusive).

As also described above, an undivided black screen 152 achieves goodmovie display, but makes flickering of the screen more noticeable. Thus,it is desirable to divide the black insert into multiple parts. However,too many divisions will cause moving pictures to blur. The number ofdivisions should be from 1 to 8 (both inclusive). More preferably, itshould be from 1 to 5 (both inclusive).

Incidentally, it is preferable that the number of divisions of a blackscreen can be varied between still pictures and moving pictures. WhenN=4, 75% is occupied by a black screen and 25% is occupied by imagedisplay. When the number of divisions is 1, a strip of black displaywhich makes up 75% is scanned vertically. When the number of divisionsis 3, three blocks are scanned, where each block consists of a blackscreen which makes up 25% and a display. screen which makes up 25/3percent. The number of divisions is increased for still pictures anddecreased for moving pictures. The switching can be done eitherautomatically according to input images (detection of moving pictures)or manually by the user. Alternatively, the switching can be doneaccording to input outlet such as video on the display apparatus.

For example, for wallpaper display or an input screen on a cell phone,the number of divisions should be 10 or more (in extreme cases, thedisplay may be turned on and off every 1 H). When displaying movingpictures in NTSC format, the number of divisions should be from 1 to 5(both inclusive). Preferably, the number of divisions can be switched inthree or more steps; for example, 0, 2, 4, 8 divisions, and so onPreferably, the ratio of the black screen to the entire display screenshould be from 0.2 to 0.9 (from 1.2 to 9 in terms of N) both inclusivewhen the area of the entire screen is taken as 1. More preferably, theratio should be from 0.25 to 0.6 (from 1.25 to 6 in terms of N) bothinclusive. If the ratio is 0.20 or less, movie display is not improvedmuch. When the ratio is 0.9 or more, the display part becomes bright andits vertical movements become liable to be recognized visually.

Also, preferably, the number of frames per second is from 10 to 100 (10Hz to 100 Hz) both inclusive. More preferably, it is from 12 to 65 (12Hz to 65 Hz) both inclusive. When the number of frames is small,flickering of the screen becomes conspicuous while too large a number offrames makes writing from the source driver circuit 14 and the likedifficult, resulting in deterioration of resolution.

The present invention allows the brightness of images to be varied bycontrolling the gate signal lines 17. However, needless to say, thebrightness of images may be varied by varying the current (voltage)applied to the source signal lines 18. It goes without saying that thetwo methods described above (FIGS. 33 and 35 and the like) may be usedin combination: the method of controlling the gate signal lines 17 andthe method of varying the current (voltage) applied to the source signallines 18.

Needless to say, the above items also apply to the pixel configurationsfor current programming in FIG. 38 and the like as well as to the pixelconfigurations for voltage programming in FIGS. 43, 51, 54, and thelike. This can be accomplished through on/off control of the transistor11 d in FIG. 38, transistor 11 d in FIG. 43, and transistor 11 e in FIG.51. In this way, by turning on and off the wiring which delivers currentto the EL elements 15, the N-fold pulse driving according to the presentinvention can be implemented easily.

Also, the gate signal line 17 b may be set to Vgl for a period of 1F/Nanytime during the period of 1F (not limited to 1F. Any unit time willdo). This is because a predetermined brightness is obtained by turningoff the EL element 15 for a predetermined period out of a unit time.However, it is preferable to set the gate signal line 17 b to Vgl andilluminate the EL element 15 immediately after the current programmingperiod (1 H). This will reduce the effect of retention characteristicsof the capacitor 19 in FIG. 1.

Also, preferably the number of screen divisions is configured to bevariable. For example, when the user presses a brightness adjustmentswitch or turns a brightness adjustment knob, the value of K may bechanged in response. Alternatively, the value of K may be changedmanually or automatically depending on images or data to be displayed.

In this way, the mechanism for changing the value of K (the number ofdivisions of the image display part 53) can be implemented easily. Thiscan be achieved by simply making the time to change ST (when to set STlow during 1F) adjustable or variable.

Incidentally, although it has been stated with reference to FIG. 16 andthe like that a period (1F/N) during which the gate signal line 17 b isset to Vgl is divided into a plurality of parts (K parts) and that aperiod of 1F/(K·N) during which the gate signal line 17 b is set to Vglrepeats K times, this is not restrictive. A period of 1F/(K·N) may berepeated L (L≠K) times. In other words, the present invention displaysthe display screen 50 by controlling the period (time) during whichcurrent is passed through the EL element 15. Thus, the idea of repeatingthe 1F/(K·N) period L (L≠K) times is included in the technical idea ofthe present invention. Also, by varying the value of L, the brightnessof the display screen 50 can be changed digitally. For example, there isa 50% change of brightness (contrast) between L=2 and L=3. The controldescribed here is also applicable to other examples of the presentinvention (of course, it is applicable to what is described laterherein). These are also included in the N-fold pulse driving accordingto the present invention.

The above examples involve placing (forming) the transistor 11 d servingas a switching element between the EL element 15 and driver transistor11 a and turning on and off the screen 50 by controlling the transistor11 d. This drive method eliminates shortages of write current in blackdisplay condition during current programming and thereby achieves properresolution or black display. That is, in current programming, it isimportant to achieve proper black display. The drive method describednext achieves proper black display by resetting the driver transistor 11a. This example will be described below with reference to FIG. 32.

The pixel configuration in FIG. 32 is basically the same as the oneshown in FIG. 1. With the pixel configuration in FIG. 32, a programmedIw current flows through the EL element 15, illuminating the EL element15. By being programmed, the driver transistor 11 a retains a capabilityto pass current. The drive system shown in FIG. 32 resets (turns off)the transistor 11 a using this capability to pass current. Hereinafter,this drive system will be referred to as reset driving.

To implement reset driving using the pixel configuration shown in FIG.1, the transistors 11 b and 11 c must be able to be switched on and offindependently of each other. Specifically, as illustrated in FIG. 32, itis necessary to be able to independently control the gate signal line 17a (gate signal line WR) used for on/off control of the transistor 11 band the gate signal line 17 c (gate signal line EL) used for on/offcontrol of the transistor 11 c. The gate signal lines 17 a and 17 c canbe controlled using two independent shift registers 61 as illustrated inFIG. 6.

Preferably, the drive voltage should be varied between the gate signalline 17 a which drives the transistor 11 b and the gate signal line 17 bwhich drives the transistor 11 d (when the pixel configuration in FIG. 1is used). The amplitude value (difference between turn-on voltage andturn-off voltage) of the gate signal line 17 a should be smaller thanthe amplitude value of the gate signal line 17 b.

Too large an amplitude value of the gate signal line 17 will increasepenetration voltage between the gate signal line 17 and pixel 16,resulting in an insufficient black level. The amplitude of the gatesignal line 17 a can be controlled by controlling the time when thepotential of the source signal line 18 is not applied (or is applied(during selection)) to the pixel 16. Since changes in the potential ofthe source signal line 18 are small, the amplitude value of the gatesignal line 17 a can be made small.

On the other hand, the gate signal line 17 b is used for on/off controlof EL. Thus, its amplitude value becomes large. For this, output voltageis varied between the shift register circuits 61 a and 61 b. If thepixel is constructed of P-channel transistors, approximately equal Vgh(turn-off voltage) is used for the shift register circuits 61 a and 61 bwhile Vgl (turn-on voltage) of the shift register circuit 61 a is madelower than Vgl (turn-on voltage) of the shift register circuit 61 b.

Reset driving will be described below with reference to FIG. 33. FIG. 33is a diagram illustrating a principle of reset driving. First, asillustrated in FIG. 33(a), the transistors 11 c and 11 d are turned offand the transistor 11 b is turned on. As a result, the drain (D)terminal and gate (G) terminal of the driver transistor 11 a areshort-circuited, allowing a current Ib to flow. Generally, thetransistor 11 a has been programmed with current in the previous field(frame) In this state, as the transistor 11 d is turned off and thetransistor 11 b is turned on, the drive current Ib flows through thegate (G) terminal of the transistor 11 a. Consequently, the gate (G)terminal and drain (D) terminal of the transistor 11 a have the samepotential, resetting the transistor 11 a (to a state in which no currentflows).

The reset mode (in which no current flows) of the transistor 11 a isequivalent to a state in which an offset voltage is held in voltageoffset canceling mode described with reference to FIG. 51 and the like.

That is, in the state in FIG. 33(a), the offset voltage is held betweenthe terminals of the capacitor 19.

The offset voltage varies with the characteristics of the transistor 11a. Thus, in FIG. 33(a), a state in which the transistor 11 a does notpass current is maintained in the capacitor 19 in each pixel (i.e., thetransistor 11 a passes a black display current close to zero).

Incidentally, before the operation in FIG. 33(a), it is preferable toturn off the transistors 11 b and 11 c, turn on the transistor 11 d, andpass current through the driver transistor 11 a. Preferably, thisoperation should be completed in a minimum time. Otherwise, there is afear that a current will flow through the EL element 15, illuminatingthe EL element 15, and thereby lowering display contrast. Preferably,the operating time here is from 0.1% to 10% of 1 H (one horizontalscanning period) both inclusive. More preferably, it is from 0.2% to 2%or from 0.2 μsec to 5 μsec (both inclusive). Also, this operation (theoperation to be performed before the operation in FIG. 33(a)) may beperformed on all the pixels 16 of the screen at once. This operationwill lower the drain (D) terminal voltage of the driver transistor 11 a,making it possible to pass the current Ib smoothly in the state shown inFIG. 33(a). Incidentally, the above items also apply to other resetdriving according to the present invention.

As the operation time of FIG. 33(a) becomes longer, a larger Ib currenttends to flow, reducing the terminal voltage of the capacitor 19. Thus,the operation time of FIG. 33(a) should be fixed. It has been shownexperimentally and analytically that preferably the operation time inFIG. 33(a) is from 1 H to 5 Hs (both inclusive).

Preferably, this period should be varied among R, G, and B pixels. Thisis because EL material varies among different colors and rising voltagevaries among different EL materials. Optimum periods suitable for ELmaterials should be specified separately for the R, G, and B pixels.Although it has been stated that the period should be from 1 H to 5 Hs(both inclusive) in this example, it goes without saying that the periodmay be 5 Hs or longer in the case of a drive system which mainlyconcerns black insertion (writing of a black screen). Incidentally, thelonger the period, the better the black display condition of pixels.

A state shown in FIG. 33(b) occurs during a period of 1 H to 5 Hs (bothinclusive) after the state in FIG. 33(a) FIG. 33(b) shows a state inwhich the transistors 11 c and 11 b are on and the transistor 11 d isoff. This is a state in which current programming is being performed, asdescribed earlier. Specifically, a programming current Iw is output (orabsorbed) from the source driver circuit 14 and passed through thedriver transistor 11 a. The potential of the gate (G) terminal of thedriver transistor 11 a is set so that the programming current Iw flows(the set potential is held in the capacitor 19).

If the programming current Iw is 0 A, the transistor 11 a is held in thestate in FIG. 33(a) in which it does not pass current, and thus a properblack display is achieved. Also, when performing current programming forwhite display in FIG. 33(b), the current programming is started fromoffset voltage of completely black display even if there are variationsin the characteristics of driver transistors in pixels. Thus, the timerequired to reach a target current value becomes uniform according togradations. This eliminates gradation errors due to variations in thecharacteristics of the transistors 11 a, making it possible to achieveproper image display.

After the programming in FIG. 33(b), the transistors 11 b and 11 c areturned off in sequence and the transistor 11 d is turned on to deliverthe programming current Iw (=Ie) to the EL element 15 from the drivertransistor 11 a, and thereby illuminate the EL element 15. What is shownin FIG. 33(c) has already been described with reference to FIG. 1 andthe like, and thus detailed description thereof will be omitted.

The drive system (reset driving) described with reference to FIG. 33consists of a first operation of disconnecting the driver transistor 11a from the EL element 15 (so that no current flows) and shorting betweenthe drain (D) terminal and gate (G) terminal of the driver transistor(or between the source (S) terminal and gate (G) terminal, or generallyspeaking, between two terminals including the gate (G) terminal of thedriver transistor) and a second operation of programming the drivertransistor with current (voltage) after the first operation. At leastthe second operation is performed after the first operation.Incidentally, for reset driving, the transistors 11 b and 11 c must beable to be controlled independently as shown in FIG. 32.

In image display mode (if instantaneous changes can be observed), thepixel row to be programmed with current is reset (black display mode)and is programmed with current after 1 H (also in black display modebecause the transistor 11 d is off). Next, current is supplied to the ELelement 15 and the pixel row illuminates at a predetermined brightness(at the programmed current). That is, the pixel row of black displaymoves from top to bottom of the screen and it should look as if theimage were rewritten at the location where the pixel row passed by.

Incidentally, although it has been stated that current programming isperformed 1 H after a reset, this period may be approximately 5 Hs orshorter. This is because it takes a relatively long time for the resetin FIG. 33(a) to be completed. If this period is 5 Hs, five pixel rowswill be displayed in black (six pixel rows including the pixel row goingthrough current programming).

Also, the number of pixel rows which are reset at a time is not limitedto one, and two or more pixel rows may be reset at a time. It is alsopossible to reset and scan two or more pixel rows at a time byoverlapping some of them. For example, if four pixel rows are reset at atime, pixel rows (1), (2), (3), and (4) are reset in the firsthorizontal scanning period (1 unit), pixel rows (3), (4), (5), and (6)are reset in the second horizontal scanning period, pixel rows (5), (6),(7), and (8) are reset in the third horizontal scanning period, andpixel rows (7), (8), (9), and (10) are reset in the fourth horizontalscanning period. Incidentally the drive operations in FIGS. 33(b) and33(c) are naturally carried out in sync with the drive operation in FIG.33(a).

Needless to say, the drive operation of FIGS. 33(b) and 33(c) may beperformed after resetting all the pixels in the screen simultaneously orduring scanning. Also, it goes without saying that pixel rows may bereset (at intervals of one or more pixel rows) in interlaced drivingmode (scanning at intervals of one or more pixel rows). Also, pixel rowsmay be reset at random. The reset driving according to the presentinvention involves operating pixel rows (i.e., controlling the verticaldirection of the screen). However, the concept of reset driving does notlimit control directions to the pixel row direction. For example, itgoes without saying that reset driving may be performed in the directionof pixel columns.

Incidentally, the reset driving in FIG. 33 can achieve better imagedisplay if combined with the N-fold pulse driving according to thepresent invention or with interlaced driving. Particularly, theconfiguration in FIG. 22 can easily implement intermittent N/K-foldpulse driving (this driving method provides two or more illuminatedareas in a screen and can be implemented easily by turning on and offthe transistor 11 d by controlling the gate signal line 17 b: this hasbeen described earlier), and thus can achieve proper image displaywithout flickering.

Needless to say, more excellent image display can be achieved bycombining with a reverse bias drive method, a precharge drive method, apenetration voltage drive method, or the like described later. Thus, itgoes without saying that reset driving can be performed in combinationwith other examples according to the present invention.

FIG. 34 is a block diagram of a display apparatus which implement resetdriving. The gate driver circuit 12 a controls the gate signal line 17 aand gate signal line 17 b in FIG. 32. By the application of on/offvoltages to the gate signal line 17 a, the transistor 11 b is turned onand off. Also, by the application of on/off voltages to the gate signalline 17 b, the transistor 11 d is turned on and off. The gate drivercircuit 12 b controls the gate signal line 17 c in FIG. 32. By theapplication of on/off voltages to the gate signal line 17 c, thetransistor 11 c is turned on and off.

Thus, the gate signal line 17 a is controlled by the gate driver circuit12 a while the gate signal line 17 c is controlled by the gate drivercircuit 12 b. This makes it possible to freely specify the time to turnon the transistor 11 b and reset the driver transistor 11 a as well asthe time to turn on the transistor 111 c and program the drivertransistor 11 a with current. Other parts of the configuration are thesame as or similar to those described earlier, and thus descriptionthereof will be omitted.

FIG. 35 is a timing chart of reset driving. While a turn-on voltage isapplied to the gate signal line 17 a to turn on the transistor 11 b andreset the driver transistor 11 a, a turn-off voltage is applied to thegate signal line 17 b to keep the transistor 11 d off. This creates thestate shown in FIG. 32(a). A current Ib flows during this period.

Although in the timing chart shown in FIG. 35, the reset time is 2 Hs(when a turn-on voltage is applied to the gate signal line 17 a and thetransistor 11 b is turned on), this is not restrictive. The reset timemay be longer than 2 Hs. If a reset can be performed very quickly, thereset time may be less than 1 H.

The duration of the reset period can be changed easily using a DATA (ST)pulse period inputted in the gate driver circuit 12. For example, ifDATA inputted in an ST terminal is set high for a period of 2 Hs, thereset period outputted for each gate signal line 17 a is 2 Hs.Similarly, if DATA inputted in the ST terminal is set high for a periodof 5 Hs, the reset period outputted for each gate signal line 17 a is 5Hs.

After a reset period of 1 H, a turn-on voltage is applied to the gatesignal line 17 c(1) of the pixel row (1). As the transistor 11 c turnson, the programming current Iw applied to the source signal line 18 iswritten into the driver transistor 11 a via the transistor 11 c.

After current programming, a turn-off voltage is applied to the gatesignal line 17 c of the pixel row (1), the transistor 11 c is turnedoff, and the pixel disconnected from the source signal line. At the sametime, a turn-off voltage is also applied to the gate signal line 17 aand the driver transistor 11 a exits the reset mode (incidentally, theuse of the term “current-programming mode” is more appropriate than theterm “reset mode” to refer to this period). On the other hand, a turn-onvoltage is applied to the gate signal line 17 b, the transistor 11 d isturned on, and the current programmed into the driver transistor 11 aflows through the EL element 15. What has been said about the pixel row(1) similarly applies to the pixel row (2) and subsequent pixel rows.Also, their operation is obvious from FIG. 35. Thus, description of (2)and subsequent pixel rows will be omitted.

In FIG. 35, the reset period has been 1 H. FIG. 36 shows an example inwhich the reset period is 5 Hs. The duration of the reset period can bechanged easily using the DATA (ST) pulse period inputted in the gatedriver circuit 12. FIG. 36 shows an example in which DATA inputted inthe ST1 terminal of the gate driver circuit 12 a is set high for aperiod of 5 Hs and the reset period outputted for each gate signal line17 a is 5 Hs. The longer the reset period, the more completely the resetis performed, resulting in a proper black display. However, displaybrightness is decreased accordingly.

In FIG. 36, the reset period has been 5 Hs. Besides, the reset mode iscontinuous. However, the reset mode need not necessarily be continuous.For example, the signal outputted from each gate signal line 17 a may beturned on and off every 1 H. Such on/off operation can be achievedeasily by operating an enable circuit (not shown) formed in the outputstage of the shift register or controlling the DATA (ST) pulses inputtedin the gate driver circuit 12.

In the circuit configuration shown in FIG. 34, the gate driver circuit12 a requires at least two shift register circuits (one for the gatesignal line 17 a, the other for the gate signal line 17 b). Thispresents a problem of an increased circuit scale of the gate drivercircuit 12 a. FIG. 37 shows an example in which the gate driver circuit12 a has only one shift register. A timing chart of output signalsresulting from operation of the circuit in FIG. 37 is shown in FIG. 35.Note that the gate signal lines 17 coming out of the gate drivercircuits 12 a and 12 b are denoted by different symbols between FIGS. 35and 37.

As can be seen from the fact that an OR circuit 371 is included in FIG.37, the output of each gate signal line 17 a is ORed with the outputfrom the preceding stage to the shift register circuit 61 a. That is,the gate signal line 17 a outputs a turn-on voltage for a period of 2Hs. On the other hand, the gate signal line 17 c outputs the output ofthe shift register circuit 61 a as it is. Thus, a turn-on voltage isapplied for a period of 1 H.

For example, if the shift register circuit 61 a outputs a high-levelsignal second, a turn-on voltage is output to the gate signal lines 17 cof the pixel 16(1), which now is in a state of being programmed withcurrent (voltage). At the same time, a turn-on voltage is also output tothe gate signal lines 17 a of the pixel 16(2), turning on the transistor11 b of the pixel 16(2) and resetting the driver transistor 11 a of thepixel 16(2).

Similarly, if the shift register circuit 61 a outputs a high-levelsignal third, a turn-on voltage is output to the gate signal lines 17 cof the pixel 16(2), which now is in a state of being programmed withcurrent (voltage). At the same time, a turn-on voltage is also output tothe gate signal lines 17 a of the pixel 16(3, turning on the transistor11 b of the pixel 16(3) and resetting the driver transistor 11 a of thepixel 16(3). Thus, the gate signal lines 17 a outputs turn-on voltagesfor a period of 2 Hs, and the gate signal lines 17 c receive a turn-onvoltage for a period of 1 H.

In programming mode, since the transistors 11 b and 11 c turn onsimultaneously (FIG. 33(b)), if the transistor 11 c turns off before thetransistor 11 b during transition to non-programming mode (FIG. 33(c),the reset mode in FIG. 33(b) occurs. To prevent this situation, thetransistor 11 c must be turned off after the transistor 11 b. For that,a turn-on voltage needs to be applied to the gate signal line 17 aearlier than the gate signal line 17 c.

The above example concerns the pixel configuration in FIG. 32(basically, in FIG. 1). However, the present invention is not limited tothis. For example, it is also applicable to current-mirror pixelconfigurations such as the one shown in FIG. 38. Incidentally, in FIG.38, by turning on and off the transistor 11 e, N-fold pulse drivingillustrated in FIGS. 13, 15, etc. can be implemented. FIG. 39 is anexplanatory diagram illustrating an example employing the current-mirrorpixel configuration shown in FIG. 38. Reset driving in thecurrent-mirror pixel configuration will be described below withreference to FIG. 39.

As shown in FIG. 39(a), the transistors 11 c and 11 e are turned off andthe transistor 11 d is turned on. Then, the drain (D) terminal and gate(G) terminal of the current-programming transistor 11 b areshort-circuited and a current Ib flows between them as shown in thefigure. Generally, the transistor 11 b has been programmed with currentin the previous field (frame) and is capable of passing current (this isnatural because the gate potential is held in the capacitor 19 for aperiod of 1F and image is displayed. However, current does not flowduring a completely black display). In this state, as the transistor 11e is turned off and the transistor 11 d is turned on, the drive currentIb flows through the gate (G) terminal of the transistor 11 a (gate (G)terminal and the drain (D) terminal are short-circuited). Consequently,the gate (G) terminal and drain (D) terminal of the transistor 11 a havethe same potential, resetting the transistor 11 a (to a state in whichno current flows). Since the driver transistor 11 b shares a common gate(G) terminal with the current-programming transistor 11 a, the drivertransistor 11 b is also reset.

The reset mode (in which no current flows) of the transistors 11 a and11 b is equivalent to a state in which a offset voltage is held involtage offset canceling mode described with reference to FIG. 51 andthe like. That is, in the state in FIG. 39(a), the offset voltage isheld between the terminals of the capacitor 19 (the offset voltage is astarting voltage at which a current starts to flow: when a voltage equalto or larger than the starting voltage is applied, a current flowsthrough the transistor 11). The offset voltage varies with thecharacteristics of the transistors 11 a and 11 b. Thus, in FIG. 39(a), astate in which the transistors 11 a and 11 b do not pass current ismaintained in the capacitor 19 in each pixel (the transistors 11 a and11 b pass a black display current close to zero, i.e., they have beenreset to the starting voltage at which a current starts to flow).

In FIG. 39(a), as the reset period becomes longer, a larger Ib currenttends to flow, reducing the terminal voltage of the capacitor 19, as inthe case of FIG. 33(a). Thus, the operation time in FIG. 39(a) should befixed. It has been shown experimentally and analytically that preferablythe operation time in FIG. 39(a) is from 1 H to 10 Hs (ten horizontalscanning periods) both inclusive. More preferably, it should be from 1 Hto 5 Hs or from 20 μsec to 2 msec (both inclusive). This also applies tothe drive system in FIG. 33.

As in the case of FIG. 33(a), if the reset mode in FIG. 39(a) issynchronized with the current-programming mode in FIG. 39(b), there isno problem because the period from the reset mode in FIG. 39(a) to thecurrent-programming mode in FIG. 39(b) is fixed (constant). That is,preferably the period from the reset mode in FIG. 33(a) or FIG. 39(a) tothe current-programming mode in FIG. 33(b) or FIG. 39(b) should be from1 H to 10 Hs (ten horizontal scanning periods) both inclusive. Morepreferably, it should be from 1 H to 5 Hs or from 20 μsec to 2 msec(both inclusive). If this period is short, the driver transistors 11 arenot reset completely. If it is too long, the driver transistor 11 isturned off completely, which means that much time is required forcurrent programming. Also, the brightness of the screen 50 is decreased.

After the state in FIG. 39(a), a state shown in FIG. 39(b) occurs. FIG.39(b) shows a state in which the transistors 11 c and 11 d are turned onand the transistor 11 e is turned off. This is a state in which currentprogramming is being performed. Specifically, a programming current Iwis output (absorbed) from the source driver circuit 14 and passedthrough the current programming transistor 11 a. The potential of thegate (G) terminal of the driver transistor 11 a is set in the capacitor19 so that the programming current Iw will flow.

If the programming current Iw is 0 A (black display), the transistor 11b is held in the state in FIG. 33(a) in which it does not pass current,and thus proper black display is achieved. Also, when performing currentprogramming for white display in FIG. 39(b), the current programming isstarted from offset voltage of completely black display even if thereare variations in the characteristics of driver transistors in pixels(the offset voltage is a starting voltage at which a current specifiedaccording to the characteristics of each driver transistor starts toflow). Thus, the time required to reach a target current value becomesuniform according to gradations. This eliminates gradation errors due tovariations in the characteristics of the transistor 11 a or 11 b, makingit possible to achieve proper image display.

After the current programming in FIG. 39(b), the transistors 11 c and 11d are turned off in sequence and the transistor 11 e is turned on todeliver the programming current Iw (=Ie) to the EL element 15 from thedriver transistor 11 b, and thereby illuminate the EL element 15. Whatis shown in FIG. 39(c) has already been described, and thus detaileddescription thereof will be omitted.

The drive system (reset driving) described with reference to FIGS. 33and 39 consists of a first operation of disconnecting the drivertransistor 11 a or 11 b from the EL element 15 (using the transistor 11e or 11 d so that no current flows) and shorting between the drain (D)terminal and gate (G) terminal of the driver transistor (or between thesource (S) terminal and gate (G) terminal, or generally speaking,between two terminals including the gate (G) terminal of the drivertransistor) and a second operation of programming the driver transistorwith current (voltage) after the first operation.

At least the second operation is performed after the first operation.Incidentally, the operation of disconnecting the driver transistor 11 aor 11 b from the EL element 15 in the first operation is not absolutelynecessary. The drain (D) terminal and gate (G) terminal of the drivertransistor are short-circuited in the first operation withoutdisconnecting the driver transistor 11 a or 11 b from the EL element 15,nothing more than some variations in reset mode may result. Whether toomit disconnection should be determined by considering thecharacteristics of the transistors in the constructed array.

The current-mirror pixel configuration in FIG. 39 provides a drivemethod which resets the current-programming transistor 11 a, andconsequently resets the driver transistor 11 b.

With the current-mirror pixel configuration in FIG. 39, it is not alwaysnecessary to disconnect the driver transistor 11 b from the EL element15 in reset mode. Thus, the following operations are performed: a firstoperation of shorting between the drain (D) terminal and gate (G)terminal of the current-programming transistor a (or between the source(S) terminal and gate (G) terminal, or generally speaking, between twoterminals including the gate (G) terminal of the current-programmingtransistor or between two terminals including the gate (G) terminal ofthe driver transistor) and a second operation of programming thecurrent-programming transistor with current (voltage) after the firstoperation. At least the second operation is performed after the firstoperation.

In image display mode (if instantaneous changes can be observed), thepixel row to be programmed with current is reset (black display mode)and is programmed with current after a predetermined H. The pixel row ofblack display moves from top to bottom of the screen and it should lookas if the image were rewritten at the location where the pixel rowpassed by.

Although the above example has been described mainly in relation topixel configuration for current programming, the reset driving accordingto the present invention can also be applied to pixel configuration forvoltage programming. FIG. 43 is an explanatory diagram illustrating apixel configuration (panel configuration) according to the presentinvention used to perform reset driving in a pixel configuration forvoltage programming.

In the configuration shown in FIG. 43, a transistor 11 e which resets adriver transistor 11 a has been formed. When a turn-on voltage isapplied to a gate signal line 17 e, the transistor 11 e turns on,causing a short circuit between the gate (G) terminal and drain (D)terminal of the driver transistor 11 a. Also a transistor 11 d whichcuts off a current path between the EL element 15 and driver transistor11 a has been formed. The reset driving according to the presentinvention in a pixel configuration for voltage programming will bedescribed below with reference to FIG. 44.

As illustrated in FIG. 44(a), the transistors 11 b and 11 d are turnedoff and the transistor 11 e is turned on. The drain (D) terminal andgate (G) terminal of the driver transistor 11 a are short-circuited anda current Ib flows as shown in the figure. Consequently, the gate (G)terminal and drain (D) terminal of the transistor 11 a have the samepotential, resetting the transistor 11 a (to a state in which no currentflows). Before resetting the transistor 11 a, the transistor 11 d isturned on, the transistor 11 e is turned off, and current is passedthrough the transistor 11 a in sync with an HD synchronization signal asdescribed with reference to FIG. 33 or 39. Then the operation shown inFIG. 44(a) is performed.

The reset mode (in which no current flows) of the transistors 11 a and11 b is equivalent to a state in which an offset voltage is held involtage offset canceling mode described with reference to FIG. 41 andthe like. That is, in the state in FIG. 44(a), the offset voltage (resetvoltage) is held between the terminals of the capacitor 19. The resetvoltage varies with the characteristics of the driver transistor 11 a.Thus, in FIG. 44(a), a state in which the driver transistors 11 a do notpass current is maintained in the capacitor 19 in each pixel (thetransistor 11 a passes a black display current close to zero, i.e., ithas been reset to the starting voltage at which a current starts toflow).

Incidentally, in the pixel configuration for voltage programming, as thereset period becomes longer, a larger Ib current tends to flow, reducingthe terminal voltage of the capacitor 19, as in the case of pixelconfiguration for current programming. Thus, the operation time in FIG.44(a) should be fixed. Preferably, the operation time should be from 0.2H to 5 Hs (five horizontal scanning periods) both inclusive. Morepreferably, it should be from 0.5 H to 4 Hs or from 2 μsec to 400 μsec(both inclusive).

Besides, it is preferable that the gate signal line 17 e should beshared with the gate signal line 17 a in a preceding stage. That is thegate signal line 17 e should be shorted to the gate signal line 17 a inthe pixel row in the preceding stage. This configuration is referred toas a preceding-stage gate control system. Incidentally, the stage-stagegate control system uses waveforms of gate signal lines of a pixel rowselected one or more Hs before the pixel row of interest. Thus, thissystem is not limited to the previous pixel row. For example, the drivertransistor 11 a of the pixel row of interest maybe reset using thewaveforms of gate signal lines two pixel rows ahead.

The stage-stage gate control system will be described more concretely.Suppose, the pixel row of interest is the (N)-th pixel row whose gatesignal lines are 17 e(N) and 17 a(N). The preceding pixel row selected 1H before is assumed to be the (N−1)-th pixel row whose gate signal linesare 17 e(N−1) and 17 a(N−1). The pixel row selected 1 H after the pixelrow of interest is assumed to be the (N+1)-th pixel row whose gatesignal lines are 17 e(N+1) and 17 a(N+1).

In the (N−1)-th H-period, as a turn-on voltage is applied to the gatesignal line 17 a(N−1) of the (N−1)-th pixel row, a turn-on voltage isalso applied to the gate signal line 17 e(N) of the (N)-th pixel row.This is because the gate signal line 17 e(N) and the gate signal line 17a(N−1) of the pixel row in the preceding stage are shorted.Consequently, the pixel transistor 11 b(N−1) in the (N−1)-th pixel rowis turned on and the voltage applied to the source signal line 18 iswritten into the gate (G) terminal of the driver transistor 11 a(N−1).At the same time, the pixel transistor 11 e(N) in the (N)-th pixel rowis turned on, the gate (G) terminal and drain (D) terminal of the drivertransistor 11 a(N) are shorted, and the driver transistor 11 a(N) isreset.

In the (N)-th H-period which follows the (N−1)-th H-period, as a turn-onvoltage is applied to the gate signal line 17 a(N) of the (N)-th pixelrow, a turn-on voltage is also applied to the gate signal line 17 e(N+1)of the (N+1)-th pixel row. Consequently, the pixel transistor 11 b(N) inthe (N)-th pixel row is turned on and the voltage applied to the sourcesignal line 18 is written into the gate (G) terminal of the drivertransistor 11 a(N). At the same time, the pixel transistor 11 e(N+1) inthe (N+1)-th pixel row is turned on, the gate (G) terminal and drain (D)terminal of the driver transistor 11 a(N+1) are shorted, and the drivertransistor 11 a(N+1) is reset.

Similarly, in the (N+1)-th period which follows the (N)-th H-period, asa turn-on voltage is applied to the gate signal line 17 a(N+1) of the(N+1)-th pixel row, a turn-on voltage is also applied to the gate signalline 17 e(N+2) of the (N+2)-th pixel row. Consequently, the pixeltransistor 11 b(N+1) in the (N+1)-th pixel row is turned on and thevoltage applied to the source signal line 18 is written into the gate(G) terminal of the driver transistor 11 a(N+1). At the same time, thepixel transistor 11 e(N+2) in the (N+2)-th pixel row is turned on, thegate (G) terminal and drain (D) terminal of the driver transistor 11a(N+2) are shorted, and the driver transistor 11 a(N+2) is reset.

According to the above-described stage-stage gate control system of thepresent invention, the driver transistor 11 a is reset for a period of 1H, and then voltage (current) programming is performed.

As in the case of FIG. 33(a), if the reset mode in FIG. 44(a) issynchronized with the voltage-programming mode in FIG. 44(b), there isno problem because the period from the reset mode in FIG. 44(a) to thecurrent-programming mode in FIG. 44(b) is fixed (constant). If thisperiod is short, the driver transistors 11 are not reset completely. Ifit is too long, the driver transistor 11 a is turned off completely,which means that much time is required for current programming. Also,the brightness of the screen 12 is decreased.

After the state in FIG. 44(a), a state shown in FIG. 44(b) occurs. FIG.44(b) shows a state in which the transistor 11 b is turned on and thetransistors 11 e and 11 d are turned off. This state in FIG. 44(b), is astate in which voltage programming is being performed. Specifically, aprogramming voltage is output from the source driver circuit 14 andwritten into the gate (G) terminal of the driver transistor 11 a (thepotential of the gate (G) terminal of the driver transistor 11 a is setin the capacitor 19). Incidentally, in the case of voltage programming,it is not always necessary to turn off the transistor 11 d duringvoltage programming. Besides, the transistor 11 e is not necessary ifthere is no need to combine with the N-fold driving shown in FIG. 13,15, or the like or perform intermittent N/K-fold pulse driving (thisdriving method provides two or more illuminated areas in a screen andcan be implemented easily by turning on and off the transistor 11 e).Since this has been described earlier, description thereof will beomitted.

When performing voltage programming for white display using theconfiguration shown in FIG. 43 or drive method shown in FIG. 44, thevoltage programming is started from offset voltage of completely blackdisplay even if there are variations in the characteristics of drivertransistors in pixels (the offset voltage is a starting voltage at whicha current specified according to the characteristics of each drivertransistor starts to flow). Thus, the time required to reach a targetcurrent value becomes uniform according to gradations. This eliminatesgradation errors due to variations in the characteristics of thetransistor 11 a, making it possible to achieve proper image display.

After the current programming in FIG. 44(b), the transistor 11 d isturned off and the transistor 11 d is turned on to deliver theprogramming current to the EL element 15 from the driver transistor 11a, and thereby illuminate the EL element 15, as shown in FIG. 44(c).

As described above, the reset driving according to the present inventionusing the voltage programming shown in FIG. 43 consists of a firstoperation of turning on the transistor 11 d, turning off the transistor11 e, and passing current through the transistor 11 a in sync with theHD synchronization signal; a second operation of disconnecting thetransistor 11 a from the EL element 15 and shorting between the drain(D) terminal and gate (G) terminal of the driver transistor 11 a (orbetween the source (S) terminal and gate (G) terminal, or generallyspeaking, between two terminals including the gate (G) terminal of thedriver transistor); and a third operation of programming the drivertransistor 11 a with voltage after the above operations.

In the above example, the transistor 11 d is turned on and off tocontrol the current delivered from the driver transistor element 11 a(in the case of configuration shown in FIG. 1) to the EL element 15. Toturn on and off the transistor 11 d, the gate signal line 17 b needs tobe scanned, for which the shift register circuit 61 (the gate drivercircuit 12) is required. However, shift register circuits 61 are largein scale and the use of a shift register circuit 61 for the gate signalline 17 b makes it impossible to reduce bezel width. A system describedwith reference to FIG. 40 solves this problem.

Incidentally, although the pixel configuration for current programmingillustrated in FIG. 1 and the like is mainly described herein by way ofexamples, the present invention is not limited to this and it goeswithout saying that the present invention can also be applied to otherconfiguration for current programming (current-mirror pixelconfiguration) described with reference to FIG. 38 and the like. Also,the technical concept of turning on and off elements as a block can alsobe applied to the pixel configuration for voltage programming in FIG. 41and the like.

According to the invention, since this method passes current through theEL elements 15 intermittently, it can be used in combination with amethod (described with reference to FIG. 50, etc.) which applies areverse bias voltage. Thus, reset driving can be performed incombination with other examples according to the present invention.

FIG. 40 shows an example of a block driving system. For ease ofunderstanding, it is assumed that a gate driver circuit 12 is formeddirectly on a board 71 or that a silicon chip, gate driver IC 12, ismounted on a board 71. Source driver circuits 14 and source signal lines18 are omitted to avoid complicating the drawing.

In FIG. 40, gate signal lines 17 a are connected to the gate drivercircuit 12. On the other hand, gate signal lines 17 b are connected toillumination control lines 401. In FIG. 40, four gate signal lines 17 bare connected to one illumination control line 401.

Incidentally, although four gate signal lines 17 b are grouped into ablock here, this is not restrictive and it goes without saying that morethan four gate signal lines 17 b may be grouped into a block. Generally,it is preferable to divide the screen 50 into five or more parts. Morepreferably, the screen 50 should be divided into ten or more parts. Evenmore preferably, the screen 50 should be divided into twenty or moreparts. A small number of divisions will make flickering conspicuous. Toolarge a number of divisions will increase the number of illuminationcontrol lines 401, making it difficult to lay out the illuminationcontrol lines 401.

Thus, in the case of a QCIF display panel, which has 220 verticalscanning lines, at least 220/5=44 or more lines should be grouped into ablock. More preferably, 220/10=11 or more lines should be grouped into ablock. However, if odd-numbered rows and even-numbered rows are groupedinto two different blocks, there is not much flickering even at a lowframe rate, and thus the two blocks are sufficient.

In the example shown in FIG. 40, the current flowing through the ELelements 15 are turned on and off on a block-by-block basis by theapplication of either a turn-on voltage (Vgl) or turn-off voltage (Vgh)to illumination control lines 401 a, 401 b, 401 c, 401 d, . . . , 401 nin sequence.

Incidentally, in the example in FIG. 40, the gate signal lines 17 b donot intersect the illumination control lines 401. Thus, there can be nodefect in which a gate signal line 17 b would become short-circuitedwith an illumination control line 401. Also, since there is nocapacitive coupling between gate signal lines 17 b and illuminationcontrol lines 401, addition of capacitance is very small when the gatesignal lines 17 b are viewed from the illumination control lines 401.This makes it easy to drive the illumination control lines 401.

The gate driver circuit 12 is connected with the gate signal lines 17 a.When a turn-on voltage is applied to gate signal lines 17 a, theappropriate pixel rows are selected and the transistors 11 b and 11 c inthe selected pixel rows are turned on. Then, currents (voltage) appliedto the source signal lines 18 are programmed into the capacitors 19 inthe pixels. On the other hand, the gate signal lines 17 b are connectedwith the gate (G) terminals of the transistors 11 d in the pixels. Thus,when a turn-on voltage (Vgl) is applied to the illumination controllines 401, current paths are formed between the driver transistors 11 aand EL elements 15. When a turn-off voltage (Vgh) is applied, the anodeterminals of the EL elements 15 are opened.

Preferably, control timing of turn-on/turn-off voltages applied to theillumination control lines 401 and a pixel row selection voltage (Vgl)outputted to the gate signal lines 17 a by the gate driver circuit 12are synchronized with one horizontal scanning clock (1H). However, thisis not restrictive.

The signals applied to the illumination control lines 401 simply turn onand off the current delivered to the EL elements 15. They do not need tobe synchronized with image data outputted from the source drivercircuits 14. This is because the signals applied to the illuminationcontrol lines 401 are intended to control the current programmed intothe capacitors 19 in the pixels 16. Thus, they do not always need to besynchronized with the pixel row selection signal. Even when they aresynchronized, the clock is not limited to a 1-H signal and may be a ½-Hor ¼-H signal.

Even in the case of the current-mirror pixel configuration shown in FIG.38, the transistors 11 e can be turned on and off if the gate signallines 17 b are connected to the illumination control lines 401. Thus,block driving can be implemented.

Incidentally, in FIG. 32, by connecting the gate signal lines 17 a tothe illumination control lines 401 and performing resets, it is possibleto implement block driving. In other words, the block driving accordingto the present invention is a drive method which puts a plurality ofpixel rows in non-illumination (black display) mode simultaneously usingone control line.

In the above example, one selection pixel row is placed (formed) perpixel row. The present invention is not limited to this and a selectiongate signal line may be placed (formed) for two or more pixel rows.

FIG. 41 shows such an example. Incidentally, for ease of explanation,the pixel configuration in FIG. 1 is employed mainly. In FIG. 41, thegate signal line 17 a for pixel row selection selects three pixels (16R,16G, and 16B) simultaneously. Reference character R is intended toindicate something related to a red pixel, reference character Gindicates something related to a green pixel, and reference character Bindicates something related to a blue pixel.

Thus, when the gate signal line 17 a is selected, the pixels 16R, 16G,and 16B are selected and get ready to write data. The pixel 16R writesdata into a capacitor 19R via a source signal line 18R, the pixel 16Gwrites data into a capacitor 19G via a source signal line 18G, and thepixel 16B writes data into a capacitor 19B via a source signal line 18B.

The transistor 11 d of the pixel 16R is connected to a gate signal line17 bR, the transistor 11 d of the pixel 16G is connected to a gatesignal line 17 bG, and the transistor 11 d of the pixel 16B is connectedto a gate signal line 17 bB. Thus, an EL element 15R of the pixel 16R,EL element 15G of the pixel 16G, and EL element 15B of the pixel 16B canbe turned on and off separately. Illumination times and illuminationperiods of the EL element 15R, EL element 15G, and EL element 15B can becontrolled separately by controlling the gate signal line 17 bR, gatesignal line 17 bG, and gate signal line 17 bB.

To implement this operation, in the configuration in FIG. 6, it isappropriate to form (place) four shift register circuits: a shiftregister circuit 61 which scans the gate signal line 17 a, shiftregister circuit 61 which scans the gate signal line 17 bR, shiftregister circuit 61 which scans the gate signal line 17 bG, and shiftregister circuit 61 which scans the gate signal line 17 bB.

Incidentally, although it has been stated that a current N times largerthan a predetermined current is passed through the source signal line 18and that a current N times larger than a predetermined current is passedthrough the EL element 15 for a period of 1/N, this cannot beimplemented in practice. Actually, signal pulses applied to the gatesignal line 17 penetrate into the capacitor 19, making it impossible toset a desired voltage value (current value) on the capacitor 19.Generally, a voltage value (current value) lower than a desired voltagevalue (current value) is set on the capacitor 19. For example, even if10 times larger current value is meant to be set, only approximately 5times larger current value is set on the capacitor 19. For example, evenif N=10 is specified, N=5 times larger current actually flows throughthe EL element 15. Thus, this method sets an N times larger currentvalue to pass a current proportional or corresponding to the N-foldvalue through the EL element 15. Alternatively, this drive methodapplies a current larger than a desired value to the EL element 15 in apulsed manner.

This method performs current (voltage) programming so as to obtaindesired emission brightness of the EL element by passing a currentlarger than a desired value intermittently through the driver transistor11 a (in the case of FIG. 1) (i.e., a current which will give brightnesshigher than the desired brightness if passed through the EL element 15continuously).

Incidentally, a compensation circuit which employs the penetration tothe capacitor 19 is installed in the source driver circuit 14. This willbe described later.

Preferably, N-channel transistors are used as the switching transistors11 b and 11 c, etc. in FIG. 1 and the like. This will reduce penetrationvoltage reaching the capacitor 19. Also, since off-leakage of thecapacitor 19 is reduced, this method can be applied to a 10-Hz or lowerframe rate.

Depending on pixel configuration, if the penetration voltage tends toincrease the current flowing through the EL element 15, white peakvoltage will increase, increasing perceived contrast in image display.This provides for a good image display.

Conversely, it is also useful to use P-channel transistors as theswitching transistors 11 b and 11 c in FIG. 1 to cause penetration, andthereby obtain a proper black display. When the P-channel transistor 11b turns off, the voltage goes high (Vgh), shifting the terminal voltageof the capacitor 19 slightly to the Vdd side. Consequently, the voltageat the gate (G) terminal of the transistor 11 a rises, resulting in moreintense black display. Also, the current used for first gradationdisplay can be increased (a certain base current can be delivered upuntil gradation 1), and thus shortages of write current can be easedduring current programming.

Another drive method according to the present invention will bedescribed below with reference to drawings. FIG. 174 is an explanatorydiagram illustrating a display panel which performs sequential drivingaccording to the present invention. A source driver circuit 14 outputsR, G, and B data to connection terminals 761 by switching among them.Thus, the source driver circuit 14 only needs ⅓ as many output terminalsas in FIG. 48.

Signals outputted from the source driver circuit 14 to the connectionterminals 761 are allocated to 18R, 18G, and 18B by an output switchingcircuit 1741. The output switching circuit 1741 is formed directly on aboard 71 by polysilicon technology. Alternatively, the output switchingcircuit 1741 may be formed with silicon chips and mounted on the board71 by COG technology. Also, the output switching circuit 1741 may beincorporated into the source driver circuit 14 as a sub-circuit of thesource driver circuit 14.

If a changeover switch 1742 is connected to an R terminal, the outputsignal from the source driver circuit 14 is applied to the source signalline 18R. If the changeover switch 1742 is connected to a G terminal,the output signal from the source driver circuit 14 is applied to thesource signal line 18G. If the changeover switch 1742 is connected to aB terminal, the output signal from the source driver circuit 14 isapplied to the source signal line 18B.

Incidentally, in the configuration in FIG. 175, when the changeoverswitch 1742 is connected to the R terminal, the G terminal and Bterminal of the changeover switch are open. Thus, the current enteringthe source signal lines 18G and 18B is 0 A. Consequently, the pixels 16connected to the source signal lines 18G and 18B provide a blackdisplay.

When the changeover switch 1742 is connected to the G terminal, the Rterminal and B terminal of the changeover switch are open. Thus, thecurrent entering the source signal lines 18R and 18B is 0 A.Consequently, the pixels 16 connected to the source signal lines 18R and18B provide a black display.

In the configuration in FIG. 175, when the changeover switch 1742 isconnected to the B terminal, the R terminal and G terminal of thechangeover switch are open. Thus, the current entering the source signallines 18R and 18G is 0 A. Consequently, the pixels 16 connected to thesource signal lines 18R and 18G provide a black display.

Basically, if one frame consists of three fields, R image data iswritten in sequence into the pixels 16 in the screen 50 in the firstfield. In the second field, G image data is written in sequence into thepixels 16 in the screen 50. In the third field, B image data is writtenin sequence into the pixels 16 in the screen 50.

Thus, R data→G data→B data→R data→ . . . are rewritten in sequence inthe appropriate fields to implement sequential driving. Description ofhow N-fold pulse driving is performed by turning on and off theswitching transistor 11 d as shown in FIG. 1 has been given withreference to FIGS. 5, 13, 16, etc. Needless to say, such a drive methodcan be combined with sequential driving. Of course, it goes withoutsaying that other drive methods according to the present invention canbe combined with sequential driving.

In the above example, it has been stated that when image data is writteninto the R pixel 16, black data is written into the G pixel and B pixel,that when image data is written into the G pixel 16, black data iswritten into the R pixel and B pixel, and that when image data iswritten into the B pixel 16, black data is written into the R pixel andG pixel. The present invention is not limited to this.

For example, when image data is written into the R pixel 16, the G pixeland B pixel may retain the image data rewritten in the previous field.This can make the screen 50 brighter. When image data is written intothe G pixel 16, the R pixel and B pixel may retain the image datarewritten in the previous field. When image data is written into the Bpixel 16, the G pixel and R pixel may retain the image data rewritten inthe previous field.

In order to retain image data in pixels other than the color pixel beingrewritten, the gate signal line 17 a can be controlled separately forthe R, G, and B pixels. For example, as illustrated in FIG. 174, a gatesignal line 17 aR can be designated as a signal line which turns on andoff the transistors 11 b and 11 c of the R pixel, a gate signal line 17aG can be designated as a signal line which turns on and off thetransistors 11 b and 11 c of the G pixel, and a gate signal line 17 aBcan be designated as a signal line which turns on and off thetransistors 11 b and 11 c of the B pixel. On the other hand, the gatesignal line 17 b can be designated as a signal line which commonly turnson and off the transistors 11 d of the R, G, and B pixels.

With the above configuration, when the source driver circuit 14 outputsR image data and the changeover switch 1742 is set to an R contact, aturn-on voltage can be applied to the gate signal line 17 aR and aturn-off voltage can be applied to the gate signal lines aG and aB.Thus, the R image data can be written into the R pixel 16 and the Gpixel 16 and R pixel 16 can retain the image data of the previous field.

When the source driver circuit 14 outputs G image data in the secondfield and the changeover switch 1742 is set to aG contact, a turn-onvoltage can be applied to the gate signal line 17 aG and a turn-offvoltage can be applied to the gate signal lines aR and aB. Thus, the Gimage data can be written into the G pixel 16 and the R pixel 16 and Bpixel 16 can retain the image data of the previous field.

When the source driver circuit 14 outputs B image data in the thirdfield and the changeover switch 1742 is set to aB contact, a turn-onvoltage can be applied to the gate signal line 17 aB and a turn-offvoltage can be applied to the gate signal line aR and aG. Thus, the Bimage data can be written into the B pixel 16 and the R pixel 16 and Gpixel 16 can retain the image data of the previous field.

In the example shown in FIG. 174, the gate signal lines 17 a are placed(formed) in such a way as to turns on and off the transistors 11 b ofthe R, G, and B pixels 16 separately. However, the present invention isnot limited to this. For example, a gate signal line 17 a common to theR, G, and B pixels 16 may be formed of placed as illustrated in FIG.175.

In relation to the configuration in FIG. 174 and the like, it has beenstated that when the R source signal line is selected by the changeoverswitch 1742, the G and B source signal lines are open. However, the openstate is an electrically floating state and is not desirable.

FIG. 175 shows a configuration in which measures are taken to eliminatesuch floating state. A terminal a of a changeover switch 1742 of anoutput switching circuit 1741 is connected to a Vaa voltage (voltage forblack display) A terminal b is connected to an output terminal of thesource driver circuit 14. The changeover switch 1742 is installed foreach of the R, G, and B pixels.

In the state shown in FIG. 175, a changeover switch 1742R is connectedto a Vaa terminal. Thus, the Vaa voltage (voltage for black display) isapplied to the source signal line 18R. A changeover switch 1742G isconnected to a Vaa terminal. Thus, the Vaa voltage (voltage for blackdisplay) is applied to the source signal line 18G. A changeover switch1742B is connected to the output terminal of the source driver circuit14. Thus, a B image signal is applied to the source signal line 18B.

In the above state, the B pixel is being rewritten and a black displayvoltage is applied to the R pixel and G pixel. As the changeoverswitches 1742 are controlled in the above manner, an image composed ofthe pixels 16 are rewritten. Incidentally, control of the gate signallines 17 b is the same as in the examples described above, and thusdetailed description thereof will be omitted.

In the above example, the R pixel 16 is rewritten in the first field,the G pixel 16 is rewritten in the second field, and the B pixel 16 isrewritten in the third field. That is, the color of the pixel rewrittenchanges every field. The present invention is not limited to this. Thecolor of the pixel rewritten may be changed every horizontal scanningperiod (1 H). For example, a possible drive method involves rewritingthe R pixel in the first H, the G pixel in the second H, the B pixel inthe third H, the R pixel in the fourth H, and so on. Of course, thecolor of the pixel rewritten may be changed every two horizontalscanning periods or every ⅓ field.

FIG. 176 shows an example, in which the color of the pixel rewrittenchanges every 1 H. Incidentally, in FIGS. 176 to 178, the obliquehatching indicates that the pixels 16 either retain image data from theprevious field instead of being rewritten or are displayed in black. Ofcourse, the black display of the pixels and retention of image data fromthe previous field may be repeated alternately.

Needless to say, in the drive system in FIGS. 174 to 178, it is alsopossible to use the N-fold pulse driving in FIG. 13 or simultaneousM-row driving. FIGS. 174 to 178 show writing of pixels 16. Althoughillumination control of the EL elements 15 is not described, it goeswithout saying that this example can be used in combination withexamples described earlier or later.

One frame need not necessarily consist of three fields and may consistof two fields or four or more fields. In one example illustrated herein,one frame consists of two fields and the R and G pixels out of the threeprimary RGB colors are rewritten in the first field and the B pixel isrewritten in the second field. In another example illustrated herein,one frame consists of four fields and the R pixel out of the threeprimary RGB colors is rewritten in the first field, the G pixel isrewritten in the second field, and the B pixel is rewritten in the thirdand fourth field. In these sequences, white balance can be achieved moreefficiently if the luminous efficiencies of the R, G, and B EL elements15 are taken into consideration.

In the above example, the R pixel 16 is rewritten in the first field,the G pixel 16 is rewritten in the second field, and the B pixel 16 isrewritten in the third field. That is, the color of the pixel rewrittenchanges every field.

According to the example shown in FIG. 176, in the first field, an Rpixel is rewritten in the first H, a G pixel is rewritten in the secondH, a B pixel is rewritten in the third H, an R pixel is rewritten in thefourth H, and so on. Of course, the color of the pixel rewritten may bechanged every two or more horizontal scanning periods or every ⅓ field.

According to the example shown in FIG. 176, in the first field, an Rpixel is rewritten in the first H, a G pixel is rewritten in the secondH, a B pixel is rewritten in the third H, and an R pixel is rewritten inthe fourth H. In the second field, a G pixel is rewritten in the firstH, a B pixel is rewritten in the second H, an R pixel is rewritten inthe third H, and a G pixel is rewritten in the fourth H. In the thirdfield, a B pixel is rewritten in the first H, an R pixel is rewritten inthe second H, a G pixel is rewritten in the third H, and a B pixel isrewritten in the fourth H.

Thus, by rewriting the R, G, and B pixels in each field arbitrarily orwith some regularity, it is possible to prevent separation among the R,G, and B colors. Also, flickering is reduced.

In FIG. 177, a plurality of pixel 16 colors are rewritten every 1 H. InFIG. 176, in the first field, the pixel 16 rewritten in the first H isan R pixel, the pixel 16 rewritten in the second H is a G pixel, thepixel 16 rewritten in the third H is a B pixel, the pixel 16 rewrittenin the fourth H is an R pixel.

In FIG. 177, positions of the different-colored pixels rewritten arechanged every 1 H. By assigning R, G, and B pixels to different fields(needless to say, this may be done with some regularity) and rewritingthem in sequence, it is possible to prevent separation among the R, G,and B colors as well as to reduce flickering.

Incidentally, even in the example in FIG. 177, the R, G, and B pixelsshould have the same illumination time or luminous intensity in eachpicture element, which is a set of R, G, and B pixels. Needless to say,this is also done in the examples in FIGS. 175, 176, and the like toavoid color irregularities.

As shown in FIG. 177, in order to rewrite pixels of different colors ineach H (three colors—R, G, and B—are rewritten in the first H in thefirst field in FIG. 177), in FIG. 174, the source driver circuit 14 canbe configured to output image signals of arbitrary colors (or colorsdetermined with some regularity) to the terminals and the changeoverswitches 1742 can be configured to connect to the R, G, and B contactsarbitrarily (or with some regularity).

The panel in an example in FIG. 178 has W (white) pixels 16W in additionto the three primary colors RGB. By forming or placing pixels 16W, it ispossible to achieve peak brightness of colors properly as well as toachieve a high brightness-display. FIG. 178(a) shows an example in whichR, G, B, and W pixels 16 are formed in each pixel row. FIG. 178(b) showsan example in which R, G, B, and W pixels are placed in turns indifferent pixel rows.

Needless to say, the drive method in FIG. 178 can incorporate the drivemethods in FIGS. 176, 177, etc. Also, it goes without saying that N-foldpulse driving, simultaneous M-row driving, etc. can be incorporated.These matters can easily be implemented by those skilled in the artbased on this specification, and thus description thereof will beomitted.

Incidentally, for ease of explanation, it is assumed that the displaypanel according to the present invention has the three primary colorsRGB, but this is not restrictive. The display panel may have cyan,yellow, and magenta in addition to R, G, and B, or it may have any oneof R, G, and B or any two of R, G, and B.

Also, although it has been stated that the sequential driving systemhandles R, G, and B in each field, it goes without saying that thepresent invention is not limited to this. Besides, the examples in FIGS.174 to 178 illustrate how image data is written into pixels 16. They donot illustrate (although, of course, they are related to) a method ofdisplaying images by operating the transistors 11 d and passing currentthrough the EL elements 15 unlike in FIG. 1. In the configuration shownin FIG. 1, current is passed through the EL elements 15 by controllingthe transistors 11 d.

Also, the drive methods in FIGS. 176, 177, etc. can display RGB imagesin sequence by controlling the transistors 11 d (in the case of FIG. 1).For example, in FIG. 179(a), an R display area 53R, G display area 53G,and B display area 53B are scanned from top to bottom (or from bottom totop) of the screen during one frame (one field) period. The remainingarea becomes a non-display area 52. That is, intermittent driving isperformed.

FIG. 179(b) shows an example in which a plurality of RGB display areas53 are generated during one field (one frame) period. This drive methodis analogous to the one shown in FIG. 16. Thus, it will require noexplanation. In FIG. 179(b), by dividing the display area 53, it ispossible to eliminate flickering even at a lower frame rate.

FIG. 180(a) shows a case in which R, G, and B display areas 53 havedifferent sizes (needless to say, the size of a display area 53 isproportional to its illumination period). In FIG. 180(a), the R displayarea 53R and G display area 53G have the same size. The B display area53B has a larger size than the G display area 53G.

With organic EL display panels, B often has a low luminous efficiency.By making the B display area 53B larger than the display areas 53 ofother colors as shown in FIG. 180(a), it is possible to achieve a whitebalance efficiently.

FIG. 180(b) shows an example in which there are a plurality of B displayperiods 53B (53B1 and 53B2) during one field (one frame) period. WhereasFIG. 180(a) shows a method of varying the size of one B display area 53Bto allow the white balance to be adjusted properly, FIG. 180(b) shows amethod of displaying multiple B display areas 53B having the samesurface area to achieve a proper white balance.

The drive system according to the present invention is not limited toeither FIG. 180(a) or FIG. 180(b). It is intended to generate R, G, andB display areas 53 and create an intermittent display, and therebycorrect blurred moving pictures and insufficient writing into the pixels16. With the drive method in FIG. 16, independent display areas 53 forR, G, and B are not generated. R, G, and B are displayed simultaneously(it should be stated that a W display area 53 is presented).Incidentally, it goes without saying that FIG. 180(a) and FIG. 180(b)may be combined. For example, it is possible to combine the drive methodof using display areas 53 of different sizes for R, G, and B in FIG.180(a) with the drive method of generating multiple display areas 53 forR, G, or B in FIG. 180(b).

Incidentally, the drive method in FIGS. 179 and 180 is not limited tothe drive methods in FIGS. 174 to 178 according to the presentinvention. Needless to say, with a configuration in which the currentsflowing through the EL elements 15 (EL elements 15R, EL elements 15G,and EL elements 15B) are controlled separately for R, G, and B as shownin FIG. 41, the drive method in FIGS. 179 and 180 can be implementedeasily. By applying turn-on/turn-off voltages to the gate signal line 17bR, it is possible to turn on and off the R pixel 16R. By applyingturn-on/turn-off voltages to the gate signal line 17 bG, it is possibleto turn on and off the G pixel 16G. By applying turn-on/turn-offvoltages to the gate signal line 17 bB, it is possible to turn on andoff the B pixel 16B.

The above driving can be implemented by forming or placing a gate drivercircuit 12 bR which controls the gate signal line 17 bR, a gate drivercircuit 12 bG which controls the gate signal line 17 bG, and a gatedriver circuit 12 bB which controls the gate signal line 17 bB, asillustrated in FIG. 181. By driving the gate drivers 12 bR, 12 bG, and12 bB in FIG. 181 by the method described in FIG. 6 or the like, thedrive method in FIGS. 179 and 180 can be implemented. Of course, it goeswithout saying that the drive methods in FIG. 16 and the like can beimplemented using the configuration of the display panel in FIG. 181.

Also, with the configuration shown in FIGS. 174 to 177, the drive methodin FIGS. 179 and 180 can be implemented using a gate signal line 17 bcommon to the R, G, and B pixels without using a gate signal line 17 bRwhich controls the EL elements 15R, a gate signal line 17 bG whichcontrols the EL elements 15G, and a gate signal line 17 bB whichcontrols the EL elements 15B as long as black image data can be writteninto pixels 16 other than the pixels 16 whose image data is rewritten.

It has been stated with reference to FIGS. 15, 18, 21, etc. that thegate signal line 17 b (EL-side selection signal line) applies a turn-onvoltage (Vgl) and turn-off voltage (Vgh) every horizontal scanningperiod (1 H). However, in the case of a constant current, light emissionquantity of the EL elements 15 is proportional to the duration of thecurrent. Thus the duration is not limited to 1 H.

FIG. 194 shows ¼-duty ratio driving. A turn-on voltage is applied to thegate signal line 17 b (EL-side selection signal line) for 1 H every 4 Hsand the locations to which the turn-on voltage is applied are scanned insync with a horizontal synchronization signal (HD).

Thus, the unit length of a conduction period is 1 H.

However, the present invention is not limited to this. The duration ofthe conduction period may be less than 1 H (½ H in FIG. 197) as shown inFIG. 197 or it may be equal to or less than 1 H.

In short, the unit length of the conduction period is not limited to 1 Hand a unit length other than 1 H can be generated easily. The OEV2circuit formed or placed in the output stage of the gate driver circuit12 b (circuit which controls the gate signal line 17 b) can be used forthat.

To introduce a concept of output enable (OEV), the following provisionsare made. By performing OEV control, turn-on and turn-off voltages (Vglvoltage and Vgh voltage) can be applied to the pixels 16 from the gatesignal line 17 a and 17 b within one horizontal scanning period (1 H).

For ease of explanation, it is assumed that in the display panelaccording to the present invention, the pixel rows to be programmed withcurrent are selected by the gate signal line 17 a (in the case of FIG.1). The output from the gate driver circuit 12 a which controls the gatesignal line 17 a is referred to as a WR-side selection signal line.Also, it is assumed that EL elements 15 are selected by the gate signalline 17 b (in the case of FIG. 1). The output from the gate drivercircuit 12 b which controls the gate signal line 17 b is referred to asan EL-side selection signal line.

The gate driver circuits 12 are fed a start pulse, which is shifted asholding data in sequence within a shift register. Based on the holdingdata in the shift register of the gate driver circuit 12 a, it isdetermined whether to output a turn-on voltage (Vgl) or turn-off voltage(Vgh) to the WR-side selection signal line. An OEV1 circuit (not shown)which turns off output forcibly is formed or placed in an output stageof the gate driver circuit 12 a. When the OEV1 circuit is low, a WR-sideselection signal which is an output of the gate driver circuit 12 a isoutput as it is to the gate signal line 17 a. The above relationship isillustrated logically in FIG. 224(a) (OR circuit). Incidentally, theturn-on voltage is set at logic level L (0) and the turn-off voltage isset at logic voltage H (1).

That is, when the gate driver circuit 12 a outputs a turn-off voltage,the turn-off voltage is applied to the gate signal line 17 a. When thegate driver circuit 12 a outputs a turn-on voltage (logic low), it isORed with the output of the OEV1 circuit by the OR circuit and theresult is output to the gate signal line 17 a. That is, when the OEV1circuit is high, the turn-off voltage (Vgh) is output to the gate driversignal line 17 a (see an exemplary timing chart in FIG. 224).

Based on holding data in a shift register of the gate driver circuit 12b, it is determined whether to output a turn-on voltage (Vgl) orturn-off voltage (Vgh) to the gate signal line 17 b (EL-side selectionsignal line). An OEV2 circuit (not shown) which turns off outputforcibly is formed or placed in an output stage of the gate drivercircuit 12 b. When the OEV2 circuit is low, an output of the gate drivercircuit 12 b is output as it is to the gate signal line 17 b. The aboverelationship is illustrated logically in FIG. 116(a). Incidentally, theturn-on voltage is set at logic level L (0) and the turn-off voltage isset at logic voltage H (1).

That is, when the gate driver circuit 12 b outputs a turn-off voltage(an EL-side selection signal is a turn-off voltage), the turn-offvoltage is applied to the gate signal line 17 b. When the gate drivercircuit 12 b outputs a turn-on voltage (logic low), it is ORed with theoutput of the OEV2 circuit by the OR circuit and the result is output tothe gate signal line 17 b. That is, when an input signal is high, theOEV2 circuit outputs the turn-off voltage (Vgh) to the gate driversignal line 17 b. Thus, even if the EL-side selection signal from theOEV2 circuit is a turn-on voltage, the turn-off voltage (Vgh) is outputforcibly to the gate signal line 17 b. Incidentally, if an input to theOEV2 circuit is low, the EL-side selection signal is output directly tothe gate signal line 17 b (see the exemplary timing chart in FIG. 176).

Incidentally, screen brightness is adjusted under the control of OEV2.There are permissible limits to changes in screen brightness. FIG. 223illustrates relationship between permissible changes (%) and screenbrightness (nt) As can be seen from FIG. 223, relatively dark imageshave small permissible changes. Thus, in performing brightnessadjustments of the screen 50 under the control of OEV2 or through dutycycle control, the brightness of the screen 50 should be taken intoconsideration. Permissible changes should be shorter when the screen isdark than when it is bright.

In FIG. 195, the conduction period of the gate signal line 17 b (EL-sideselection signal line) does not have a unit length of 1 H. A turn-onvoltage little shorter than 1 H is applied to the gate signal lines 17 b(EL-side selection signal lines) in odd-numbered pixel rows. A turn-onvoltage is applied to the gate signal lines 17 b (EL-side selectionsignal lines) in even-numbered pixel rows for a very short period. Theduration T1 of the turn-on voltage applied to the gate signal lines 17 b(EL-side selection signal lines) in odd-numbered pixel rows plus theduration T2 of the turn-on voltage applied to the gate signal lines 17 b(EL-side selection signal lines) in even-numbered pixel rows is designedto be 1 H. FIG. 195 shows a state of the first field.

In the second field which follows the first field, a turn-on voltagelittle shorter than 1 H is applied to the gate signal lines 17 b(EL-side selection signal lines) in even-numbered pixel rows. A turn-onvoltage is applied to the gate signal lines 17 b (EL-side selectionsignal lines) in odd-numbered pixel rows for a very short period. Theduration T1 of the turn-on voltage applied to the gate signal lines 17 b(EL-side selection signal lines) in even-numbered pixel rows plus theduration T2 of the turn-on voltage applied to the gate signal lines 17 b(EL-side selection signal lines) in odd-numbered pixel rows is designedto be 1 H.

The sum duration of turn-on voltage applications to gate signal lines 17b in a plurality of pixel rows may be designed to be constant.Alternatively, the illumination time of each EL element 15 in each pixelrow in each field may be designed to be constant.

FIG. 196 shows a case in which the conduction period of the gate signalline 17 b (EL-side selection signal line) is 1.5 Hs. The rise and fallof the gate signal line 17 b at point A are designed to overlap. Thegate signal line 17 b (EL-side selection signal line) and source signalline 18 are coupled. Thus, any change in a waveform of the gate signalline 17 b (EL-side selection signal line) penetrates to the sourcesignal line 18. Consequently, any potential fluctuation in the sourcesignal line 18 lowers accuracy of current (voltage) programming, causingirregularities in the characteristics of the driver transistors 11 a toappear in the display.

Referring to FIG. 196, at point A, the voltage applied to the gatesignal line 17B (EL-side selection signal line) (1) changes from turn-onvoltage (Vgl) to turn-off voltage (Vgh). The voltage applied to the gatesignal line 17B (EL-side selection signal line) (2) changes fromturn-off voltage (Vgh) to turn-on voltage (Vgl). Thus, at point A, thesignal waveform of the gate signal line 17B (EL-side selection signalline) (1) and the signal waveform of the gate signal line 17B (EL-sideselection signal line) (2) cancel out each other. Consequently, even ifthe gate signal line 17B (EL-side selection signal line) and sourcesignal line 18 are coupled, changes in the waveform of the gate signalline 17 b (EL-side selection signal line) do not penetrate to the sourcesignal line 18. This improves the accuracy of current (voltage)programming, resulting in a uniform image display.

Incidentally, in the example in FIG. 196, the conduction period is 1.5Hs. However, the present invention is not limited to this. Needless tosay, the duration of application of the turn-on voltage may be 1 H orless as illustrated in FIG. 198.

By adjusting the duration of application of the turn-on voltage to thegate signal line 17B (EL-side selection signal line), it is possible toadjust the brightness of the display screen 50 linearly. This can bedone easily through control of the OEV2 circuit. Referring to FIG. 199,for example, display brightness in FIG. 199(b) is lower than in FIG.199(a). Also, display brightness in FIG. 199(c) is lower than in FIG.199(b).

As shown in FIG. 200, multiple sets of turn-on voltage and turn-offvoltage may be applied in a period of 1 H. FIG. 200(a) shows an examplein which six sets are applied. FIG. 200(b) shows an example in whichthree sets are applied. FIG. 200(c) shows an example in which one set isapplied. In FIG. 200, display brightness is lower in FIG. 200(b) than inFIG. 200(a). It is lower in FIG. 200(c) than in FIG. 200(b). Thus, bycontrolling the number of conduction periods, display brightness can beadjusted (controlled) easily.

One of the problems with the N-fold pulse driving according to thepresent invention is that a current N times larger than in the case ofthe conventional is applied to the EL element 15 althoughinstantaneously. A large current may lower the life of the EL element.To solve this problem, it maybe useful to apply a reverse bias voltageVm to the EL element.

Application of a reverse bias voltage means application of a reversecurrent, and thus injected electrons and positive holes are drawn to thenegative and positive poles, respectively. This makes it possible tocancel formation of space charge in the organic layer and reduceelectro-chemical degradation, thereby prolonging the life.

FIG. 45 shows reverse bias voltage Vm versus changes in terminal voltageof the EL element 15. The terminal voltage results when a rated currentis applied to the EL element 15. In FIG. 45, the current density of thecurrent passed through the EL element 15 is 100 A per square meter. Thetrend in FIG. 45 shows little difference from the trend observed whenthe current density is 50 to 100 A per square meter. Thus, it ispresumed that this method can be applied to a wide range of currentdensity.

The vertical axis represents the ratio of the terminal voltage after2500 hours to the initial terminal voltage of the EL element 15.

For example, if the terminal voltage is 8V and 10V, respectively, when acurrent with a current density of 100 A per square meter is applied attime 0 (zero) and after 2500 hours, the terminal voltage ratio is10/8=1.25.

The horizontal axis represents the ratio of the product of the reversebias voltage Vm and its application duration t1 in a period to a ratedterminal voltage V0. For example, if the reverse bias voltage Vm isapplied at 60 Hz (60 Hz has no particular meaning) for ½ (half) aperiod, then t1=0.5. Also, if the terminal voltage (rated terminalvoltage) is 8 V when a current with a current density of 100 A persquare meter is applied at time 0 (zero) and if the reverse bias voltageVm is 8 V, then |reverse bias voltage×t1/(rated terminal voltage×t2)=|−8(V)×0.5|/(8 (V)×0.5)=1.0.

In FIG. 45, the terminal voltage ratio stops to change when |reversebias voltage×t1|/(rated terminal voltage×t2) is 1.0 or larger (no changeto the initial rated terminal voltage). Consequently, the application ofthe reverse bias voltage Vm works well. However, the terminal voltageratio tends to increase when |reverse bias voltage×t1|/(rated terminalvoltage×t2) is 1.75 or larger. Thus, the reverse bias voltage Vm and theapplication duration rate t1 (or t2 or the ratio between t1 and t2)should be determined in such a way as to make |reverse biasvoltage×t1|/(rated terminal voltage×t2) equal to or larger than 1.0.Preferably, the reverse bias voltage Vm and the application durationrate t1 should be determined in such a way as to make |reverse biasvoltage×t1|(rated terminal voltage>t2) equal to or smaller than 1.75.

However, for bias driving, the reverse bias Vm and rated current shouldbe applied alternately. To equalize average brightness of samples A andB over a unit time as shown in FIG. 46 by the application of the reversebias voltage Vm, it is necessary to pass a larger currentinstantaneously than when no reverse bias voltage is applied.Consequently, the application of the reverse bias voltage Vm (sample Ain FIG. 46) also increases the terminal voltage of the EL element 15.

However, in FIG. 45, even with the drive method which involves applyingthe reverse bias voltage, the rated terminal voltage V0 should satisfythe average brightness (i.e., illuminate the EL element 15). (Accordingto examples cited herein, such a terminal voltage is obtained when acurrent with a current density of 200 A per square meter is applied.However, since the duty ratio is 1/2 the average brightness over onecycle is equal to the brightness at a current density of 200 A persquare meter.)

Generally, in the case of video display, the current applied to (passedthrough) each EL element 15 is approximately 0.2 of a white peak current(a current which flows at a rated terminal voltage, or a current with acurrent density of 100 A per square meter according to examples citedherein).

Therefore, for video display in the example in FIG. 45, the value of thehorizontal axis should be multiplied by 0.2. Thus, the reverse biasvoltage Vm and the application duration rate t1 (or t2 or the ratiobetween t1 and t2) should be determined in such a way as to make|reverse bias voltage×t1|/(rated terminal voltage×t2) equal to 0.2 orlarger. Preferably, the reverse bias voltage Vm and the applicationduration rate t1 should be determined in such a way as to make |reversebias voltage×t1|/(rated terminal voltage×t2) equal to 0.35 (=1.75×0.2)or smaller.

That is, on the horizontal axis (|reverse bias voltage×t1|/(ratedterminal voltage×t2)) in FIG. 45, the value of 1.0 should be changed to0.2. Thus, if video is displayed on the display panel (probably this isnormally the case and white raster is not likely to be displayedconstantly), the reverse bias voltage Vm should be applied for apredetermined time t1 in such a way as to make |reverse biasvoltage×t1|/(rated terminal voltage×t2) equal to 0.2 or larger. Even ifthe value of |reverse bias voltage×t1|/(rated terminal voltage×t2) isincreased, the terminal voltage ratio does not increase greatly as shownin FIG. 45. Thus, an upper limit should be set to make |reverse biasvoltage×t1|/(rated terminal voltage×t2) equal to 1.75 or smaller byallowing for white raster display.

The reverse bias driving according to the present invention will bedescribed below with reference to drawings. In a pixel configuration forreverse bias driving, an N-channel transistor 11 g is used as shown inFIG. 47. Of course, this may be a P-channel transistor.

In FIG. 47, as the voltage applied to a gate potential control line 473is set higher than the voltage applied to a reverse bias line 471, thetransistor 11 g (N) turns on and the reverse bias voltage Vm is appliedto the anode electrode of the EL element 15.

In the pixel configuration in FIG. 47 and the like, the gate potentialcontrol line 473 may be operated constantly at a fixed potential. Forexample, in FIG. 47, when voltage Vk is 0 (V), the potential of the gatepotential control line 473 is set to 0 (V) or higher (preferably, 2 V orhigher). Incidentally, this potential is denoted by Vsg. In this state,as the potential of the reverse bias line 471 is set to the reverse biasvoltage Vm (0 V or lower, and preferably −5 V or lower than Vk), thetransistor 11 g (N) turns on and the reverse bias voltage Vm is appliedto the anode electrode of the EL element 15. As the voltage of thereverse bias line 471 is set higher than the voltage applied to the gatepotential control line 473 (i.e., the gate (G) terminal voltage of thetransistor 11 g), the transistor 11 g stays off and the reverse biasvoltage Vm is not applied to the anode electrode of the EL element 15.Of course, it goes without saying that in this state, the reverse biasline 471 may be put into a high-impedance state (such as an open state).

Also, a gate driver circuit 12 c may be formed or placed separately tocontrol the reverse bias line 471 as illustrated in FIG. 48. The gatedriver circuit 12 coperates by shifting in sequence as in the case of thegate driver circuit 12 a and the location of application of the reversebias voltage is shifted in sync with the shift operation.

The drive method described above makes it possible to apply the reversebias voltage Vm to the EL element 15 by varying only the potential ofthe reverse bias line 471 with the gate (G) terminal of the transistor11 g set at a fixed potential. This makes it easy to control theapplication of the reverse bias voltage Vm.

The reverse bias voltage Vm is applied when current is not passedthrough the EL element 15. This can be done by turning on the transistor11 g when the transistor 11 d is off. That is, the reverse of on/offlogic of the transistor 11 d can be applied to the gate potentialcontrol line 473. For example, in FIG. 47, the gate (G) terminal of thetransistors 11 d and 11 g can be connected to the gate signal line 17 b.Since the transistor 11 d is a P-channel transistor and the transistor11 g is an N-channel transistor, they turn on and off in the oppositemanner.

FIG. 49 is a timing chart of reverse bias driving. In the chart, thesubscripts such as (1) and (2) indicate pixel row numbers. It is assumedfor ease of explanation that (1) indicates the first pixel row while (2)indicates the second pixel row, but this is not restrictive. It is alsopossible to consider that (1) indicates the N-th pixel row while (2)indicates the (N+1)-th pixel row. The same applies to other examplesexcept for some special cases. Although examples in FIG. 49 and the likeare described by citing the pixel configuration in FIG. 1 and the like,this is not restrictive. They are also applicable, for example, to thepixel configurations in FIGS. 41, 38, etc.

When a turn-on voltage (Vgl) is applied to the gate signal line 17 a(1)in the first pixel row, a turn-off voltage (Vgh) is applied to the gatesignal line 17 b(1) in the first pixel row. Thus, the transistor 11 d isoff and current does not flow through the EL element 15.

A voltage Vsl (which turns on the transistor 11 g) is applied to areverse bias line 471(1). Thus, the transistor 11 d is on and a reversebias voltage is applied to the EL element 15. The reverse bias voltageis applied a predetermined period (1/200 of 1 H or longer; or 0.5 μsec)after the turn-off voltage (Vgh) is applied to the gate signal line 17b. The reverse bias voltage is turned off a predetermined period (1/200of 1 H or longer; or 0.5 μsec) before the turn-on voltage (Vgl) isapplied to the gate signal line 17 b. This is done in order to preventthe transistors 11 d and 11 g from turning on simultaneously.

In the next 1 H (horizontal scanning period), a turn-off voltage (Vgh)is applied to the gate signal line 17 a, and the second pixel row isselected. That is, a turn-on voltage is applied to a gate signal line 17b(2). On the other hand, a turn-on voltage (Vgl) is applied to the gatesignal line 17 b, the transistor 11 d is turned on, and a current fromthe transistor 11 a flows through the EL element 15, causing the ELelement 15 to emit light. Also, a turn-off voltage (Vsh) is applied tothe reverse bias line 471(1) stopping the reverse bias voltage frombeing applied to the EL elements 15 in the first pixel row (1). Thevoltage Vsl (reverse bias voltage) is applied to a reverse bias line471(2) in the second pixel row.

As the above operations are repeated in sequence the images on theentire screen is rewritten. In the above example, a reverse bias voltageis applied while the pixels are being programmed. However, the circuitconfiguration in FIG. 48 is not limited to this. It is obvious that areverse bias voltage may be applied to a plurality of pixel rowscontinuously. It is also obvious that the reverse bias driving may beused in combination with block driving (see FIG. 40), N-fold pulsedriving, reset driving, or dummy pixel driving.

Reverse bias voltage can be applied not only during image display.

The reverse bias voltage may be applied for a predetermined period afterthe EL display apparatus is turned off.

Although the above example has been described with reference to thepixel configuration in FIG. 1, it goes without saying that the use ofreverse bias voltage is also applicable to the pixel configurations inFIGS. 38 and 41 and the like. For example, FIG. 50 shows a pixelconfiguration for current programming.

FIG. 50 shows a pixel configuration of a current mirror. The transistor11 d turns on 1 H (horizontal scanning period, i.e., one pixel row) ormore before the given pixel is selected. Preferably, it turns on atleast 3 Hs before. In that case, the transistor 11 d turns on 3 Hsbefore selection of the pixel, short-circuiting the gate (G) terminaland drain (D) terminal of the transistor 11 a. Consequently, thetransistor 11 a is turned off. Thus, the current stops flowing throughthe transistor 11 b and the EL element 15 is turned off.

When the EL element 15 is not illuminated, the transistor 11 g turns on,applying a reverse bias voltage to the EL element 15. Thus, the reversebias voltage is applied while the transistor 11 d is on. Consequently,the transistor 11 d and transistor 11 g turn on simultaneously inlogical terms.

The voltage Vsg is applied continuously to the gate (G) terminal of thetransistor 11 g.

The transistor 11 g turns on when a reverse bias voltage sufficientlysmaller than the voltage Vsg is applied to the reverse bias line 471.

Subsequently, when there comes a horizontal scanning period in which avideo signal is applied to (written into) the pixel, a turn-on voltageis applied to a gate signal line 17 a 1, turning on the transistor 11 c.

Thus, a video signal voltage outputted from the source driver circuit 14to the source signal line 18 is applied to the capacitor 19 (thetransistor 11 d remains on).

When the transistor 11 d is turned on, the pixel is put into blackdisplay mode.

The longer the conduction period of the transistor 11 d in one field(one frame) period, the larger the proportion of the black displayperiod. Thus, the brightness during a display period needs to beincreased to obtain a desired average brightness over one field (oneframe) in spite of the black display period. That is, the current to bepassed through the EL element 15 during the display period needs to beincreased. This operation is based on the N-fold pulse driving accordingto the present invention. Thus, an operation characteristic of thepresent invention is implemented by a combination of the N-fold pulsedriving and driving which involves creating a black display by turningon the transistor 11 d. Also, a configuration (method) characteristic ofthe present invention involves applying a reverse bias voltage to the ELelement 15 when the EL element 15 is not illuminated.

The N-fold pulse driving allows a predetermined current (programmedcurrent (at a voltage held in the capacitor 19)) to be passed throughthe EL element 15 again during one field (one frame) period even after ablack display is created once. With the configuration in FIG. 50,however, once the transistor 11 d turns on, since the capacitor 19 isdischarged (or its charge is reduced), it is not possible to pass apredetermined current (programmed current) through the EL element 15.However, this configuration features ease of circuit operation.

Incidentally, although the above example uses a pixel configuration forcurrent programming, the present invention is not limited to this and isapplicable to other current-based pixel configurations such as thoseshown in FIGS. 38 and 50. It is also applicable to a pixel configurationfor voltage programming such as the one shown in FIGS. 51, 54, and 62.

FIG. 51 shows typically one of the simplest pixel configurations forvoltage programming. The transistor 11 b acts as a selection switchingelement while the transistor 11 a acts as a driver transistor whichapplies current to the EL element 15. This configuration contains atransistor (switching element) 11 g which applies a reverse bias voltageto the anode of the EL element 15.

With the pixel configuration in FIG. 51, the current to be passedthrough the EL element 15 is applied to the source signal line 18. Then,it is applied to the gate (G) terminal of the transistor 11 a as thetransistor 11 b is selected.

To describe the configuration in FIG. 51, basic operation will bedescribed first with reference to FIG. 52. The pixel configuration inFIG. 51 is of a voltage offset canceling type and operates in fourstages: initialization operation, reset operation, programmingoperation, and light-emitting operation.

The initialization operation is performed after a horizontalsynchronization signal (HD) is provided. A turn-on voltage is applied tothe gate signal line 17 b, turning on the transistor 11 g. Besides, aturn-on voltage is also applied to the gate signal line 17 a, turning onthe transistor 11 c. At this time, a voltage Vdd is applied to thesource signal line 18. Thus, the voltage Vdd is applied to a terminal aof the capacitor 19 b. In this state, the driver transistor 11 a turnson and a small current flows through the EL element 15. This currentmakes the voltage on the drain (D) terminal of the driver transistor 11a larger in absolute value than at least the voltage at an operatingpoint of the driver transistor 11 a.

Next, the reset operation is performed. A turn-off voltage is applied tothe gate signal line 17 b, turning off the transistor 11 e. On the otherhand, a turn-on voltage is applied to the gate signal line 17 c for aperiod of T1, turning on the transistor 11 b. The period T1 correspondsto a reset period. A turn-on voltage is applied to the gate signal line17 a continuously for a period of 1 H. Preferably, the period T1 isbetween 20% and 90% (both inclusive) of 1 H or between 20 μsec and 160μsec (both inclusive). Preferably, a capacitance ratio Ca/Cb between acapacitor 19 b (Cb) and capacitor 19 a (Ca) is between 1/6 and 2/1 (bothinclusive) During a reset period, the transistor 11 b turns on,short-circuiting the gate (G) terminal and drain (D) terminal of thedriver transistor 11 a. Thus, the voltages at the gate (G) terminal anddrain (D) terminal of the transistor 11 a become equal, putting thetransistor 11 a in an offset mode (reset mode: a state in which nocurrent flows). In the reset mode, the voltage at the gate (G) terminalof the transistor 11 a approaches a starting voltage at which a currentstarts to flow. A gate voltage which maintains the reset mode is held ata terminal b of the capacitor 19 b. Thus, the capacitor 19 holds anoffset voltage (reset voltage).

In a next programming mode, a turn-off voltage is applied to the gatesignal line 17 c, turning off the transistor 11 b. On the other hand,DATA voltage is applied to the source signal line 18 for a period of Td.Thus, the sum of the DATA voltage and offset voltage (reset voltage) isapplied to the gate (G) terminal of the driver transistor 11 a. Thisallows the driver transistor 11 a to pass a programmed current.

After the programming period, a turn-off voltage is applied to the gatesignal line 17 a, turning off the transistor 11 c and cutting off thedriver transistor 11 a from the source signal line 18. Besides, aturn-off voltage is also applied to the gate signal line 17 c, turningoff the transistor 11 b, which remains off for a period of 1F. On theother hand, a turn-on voltage and turn-off voltage are applied to thegate signal line 17 b periodically, as required. Thus, if combined withN-fold pulse driving in FIGS. 13, 15, etc. or with interlaced driving,this method can achieve even better image display.

With the drive system in FIG. 52, in reset mode, the capacitor 19 holdsa starting current voltage (offset voltage, reset voltage) of thetransistor 11 a. Thus, the darkest black display is created when thereset voltage is being applied to the gate (G) terminal of the drivertransistor 11 a. However, coupling between the source signal line 18 andpixel 16, penetration voltage to the capacitor 19, or punch-through of atransistor causes excessive brightness (reduced contrast) resulting in awhitish screen. Therefore, the drive method described with reference toFIG. 53 cannot achieve high display contrast.

To apply the reverse bias voltage Vm to the EL element 15, it isnecessary to turn off the transistor 11 a. To turn off the transistor 11a, the Vdd terminal and gate (G) terminal of the transistor 11 a can beshort-circuited. This configuration will be described with reference toFIG. 53 later.

Alternatively, it is possible to apply the Vdd voltage or a voltagewhich turns off the transistor 11 a to the source signal line 18, turnon the transistor 11 b, and apply the voltage to the gate (G) terminalof the transistor 11 a. This voltage turns off the transistor 11 a (ormakes it pass almost no current (almost off: the transistor 11 a is in ahigh-impedance state)). Subsequently, the transistor 11 g is turned onand a reverse bias voltage is applied to the EL element 15.

Next, reset driving in the pixel configuration in FIG. 51 will bedescribed. FIG. 53 shows an example. As shown in FIG. 53, the gatesignal line 17 a connected to the gate (G) terminal of the transistor 11c in a pixel 16 a is also connected to the gate (G) terminal of thereset transistor 11 b in a pixel 16 b in the next stage. Similarly, thegate signal line 17 a connected to the gate (G) terminal of thetransistor 11 c in the pixel 16 b is also connected to the gate (G)terminal of the reset transistor 11 b in a pixel 16 c in the next stage.

Thus, when a turn-on voltage is applied to the gate signal line 17 aconnected to the gate (G) terminal of the transistor 11 c in the pixel16 a, the pixel 16 a enters voltage programming mode, the resettransistor 11 b of the pixel 16 b in the next stage turns on, and thedriver transistor 11 a of the pixel 16 b is reset. Similarly, when aturn-on voltage is applied to the gate signal line 17 a connected to thegate (G) terminal of the transistor 11 c in the pixel 16 b, the pixel 16b enters current programming mode, the reset transistor 11 b of thepixel 16 c in the next stage turns on, and the driver transistor 11 a ofthe pixel 16 c is reset. Thus, reset driving by way of a preceding-stagegate control system can be implemented easily. Also, the number of leadsfrom a gate signal line per pixel can be reduced.

More detailed description will be provided. Suppose voltage is appliedto gate signal lines 17 as shown in FIG. 53(a). Specifically, a turn-onvoltage is applied to the gate signal line 17 a of the pixel 16 a and aturn-off voltage is applied to the gate signal lines 17 a of otherpixels 16. Also, a turn-off voltage is applied to the gate signal lines17 b of the pixels 16 a and 16 b while a turn-on voltage is applied tothe gate signal lines 17 b of the pixels 16 c and 16 d.

In this state, the pixel 16 a is in voltage programming mode and is notilluminated, the pixel 16 b is in reset mode and not illuminated, thepixel 16 c is pending current programming and is illuminated, and thepixel 16 d is pending current programming and is illuminated.

After 1 H, data in a shift register 61 circuit of the controlling gatedriver circuit 12 is shifted one bit to enter a state shown in FIG.53(b). In FIG. 53(b), the pixel 16 a is pending current programming andis illuminated, the pixel 16 b is current programming mode and is notilluminated, the pixel 16 c is in reset mode and is not illuminated, andthe pixel 16 d is pending programming and is illuminated.

Thus, it can be seen that the voltage applied to the gate signal line 17a of each pixel resets the driver transistor 11 a of the pixel in thenext stage to perform voltage programming in the next horizontalscanning period sequentially.

The pixel configuration for voltage programming in FIG. 43 can alsoimplement preceding-stage gate control. FIG. 54 shows an example inwhich a connection method of a preceding-stage gate control system isused for the pixel configuration in FIG. 43.

In FIG. 54, the gate signal line 17 a connected to the gate (G) terminalof the transistor 11 b in the pixel 16 a is connected to the gate (G)terminal of the reset transistor 11 e in the pixel 16 b in the nextstage. Similarly, the gate signal line 17 a connected to the gate (G)terminal of the transistor 11 b in the pixel 16 b is connected to thegate (G) terminal of the reset transistor 11 e in the pixel 16 c in thenext stage.

Thus, when a turn-on voltage is applied to the gate signal line 17 aconnected to the gate (G) terminal of the transistor 11 b in the pixel16 a, the pixel 16 a enters voltage programming mode, the resettransistor 11 e of the pixel 16 b in the next stage turns on, and thedriver transistor 11 a of the pixel 16 b is reset. Similarly, when aturn-on voltage is applied to the gate signal line 17 a connected to thegate (G) terminal of the transistor 11 b in the pixel 16 b, the pixel 16b enters current programming mode, the reset transistor 11 e of thepixel 16 c in the next stage turns on, and the driver transistor 11 a ofthe pixel 16 c is reset. Thus, reset driving by way of a preceding-stagegate control system can be implemented easily.

More detailed description will be provided. Suppose voltage is appliedto gate signal lines 17 as shown in FIG. 55(a). Specifically, a turn-onvoltage is applied to the gate signal line 17 a of the pixel 16 a and aturn-off voltage is applied to the gate signal lines 17 a of otherpixels 16. It is assumed that all the transistors 11 g for reversebiasing are off.

In this state, the pixel 16 a is in voltage programming mode, the pixel16 b is in reset mode, the pixel 16 c is pending current programming,and the pixel 16 d is pending current programming.

After 1 H, data in the shift register 61 circuit of the controlling gatedriver circuit 12 is shifted one bit to enter a state shown in FIG.55(b). In FIG. 55(b), the pixel 16 a is pending current programming, thepixel 16 b is in current programming mode, the pixel 16 c is in resetmode, and the pixel 16 d is pending programming.

Thus, it can be seen that the voltage applied to the previous stage forthe gate signal line 17 a of each pixel resets the driver transistor 11a of the pixel in the next stage to perform voltage programming in thenext horizontal scanning period sequentially.

For completely black display in current driving, the driver transistors11 of the pixels are programmed with 0 current. That is, the sourcedriver circuit 14 delivers no current. When no current is delivered,parasitic capacitance caused in the source signal line 18 cannot bedischarged and the potential of the source signal line 18 cannot bevaried. Consequently, the gate potential of the driver transistors alsoremains unchanged and the potential in the previous frame (field) (1 F)remains accumulated in the capacitor 19. For example, if the previousframe contains white display, the white display is retained even if thecurrent frame contains completely black display.

To solve this problem, according to the present invention, a black levelvoltage is written into the source signal line 18 at the beginning ofone horizontal scanning period (1 H) before the current to be programmedis output to the source signal line 18. For example, if image dataconsists of the 0th to 7th gradations close to black level, a blacklevel voltage is written only during a certain period at the beginningof one horizontal scanning period to reduce the load of currentprogramming and make up for insufficient writing.

Incidentally, completely black display corresponds to the 0th gradationand white display corresponds to the 63rd gradation (in the case of64-gradation display). Precharging will be described in detail later.

The current-driven source driver IC (circuit) 14 according to thepresent invention will be described below. The source driver ICaccording to the present invention is used to implement the drivemethods and drive circuits according to the present invention describedearlier. It is used in combination with drive methods, drive circuits,and display apparatus according to the present invention. Incidentally,although the source driver circuit will be described as an IC chip, thisis not restrictive and the source driver circuit may be built on thedisplay panel using low-temperature polysilicon technology, or the like.

First, an example of a conventional current-driven source driver circuitis shown in FIG. 72, which provides a principle needed to describecurrent-driven source driver IC (source driver circuit)-according to thepresent invention.

In FIG. 72, reference numeral 721 denotes a D/A converter. The D/Aconverter 721 is fed an n-bit data signal and outputs an analog signalbased on the inputted data. The analog signal enters an operationalamplifier 722, which feeds into an N-channel transistor 631 a. Currentflowing through the N-channel transistor 631 a flows to a resister 691.A terminal voltage of the register R provides a negative input to theoperational amplifier 722. The voltage at the negative terminal equalsthe voltage at the positive terminal of the operational amplifier 722.Thus, the output voltage of the D/A converter 721 equals the terminalvoltage of the resister 691.

If the resistance of the resister 691 is 1 MΩ and the output of the D/Aconverter 721 is 1 (V), a current of 1 (V)/1 MΩ=1 (μA) flows through theresister 691, forming a constant current circuit. Thus, analog output ofthe D/A converter 721 varies with the value of data signal, and apredetermined current flows through the resister 691 according to theanalog output to provide a programming current Iw.

However, the D/A converter circuit 721 has a large circuit scale. Sodoes the operational amplifier 722. Formation of the D/A convertercircuit 721 and operational amplifier 722 in a single output circuitresults in a huge source driver IC 14, which is practically impossibleto build.

The present invention has been made in view of the above point. Thesource driver circuit 14 according to the present invention has acircuit configuration and layout configuration which reduces the scaleof a current output circuit and minimizes variations in output currentamong current output terminals.

FIG. 63 is a block diagram showing a current-driven source driver IC(circuit) 14 according to the present invention. FIG. 63 shows amulti-stage current mirror circuit comprising three-stage currentsources (631, 632, 633).

In FIG. 63, the current value of the current source 631 in the firststage is copied by the current mirror circuit to N current sources 632in the second stage (where N is an arbitrary integer). The currentvalues of the second-stage current sources 632 are copied by the currentmirror circuit to M current sources 633 in the third stage (where M isan arbitrary integer). Consequently, this configuration causes thecurrent value of the first-stage current source 631 to be copied to N×Mthird-stage current sources 633.

For example, when driving the source signal lines 18 with one driver IC14, there are 176 outputs (because the source signal lines require atotal of 176 outputs for R, G, and B) Here it is assumed that N=16 andM=11. Thus, 16×11=176 and the 176 outputs can be covered. In this way,by using a multiple of 8 or 16 for N or M, it becomes easier to lay outand design the current sources of the driver IC.

The current-driven source driver IC (circuit) 14 employing themulti-stage current mirror circuit according to the present inventioncan absorb variations in transistor characteristics because it has thesecond-stage current sources 632 in between instead of copying thecurrent value of the first-stage current source 631 directly to N×Mthird-stage current sources 633 using the current mirror circuit.

In particular, the present invention is characterized in that afirst-stage current mirror circuit (current source 631) and second-stagecurrent mirror circuits (current sources 632) are placed close to eachother. If a first-stage current source 631 are connected withthird-stage current sources 633 (i.e., in the case of two-stage currentmirror circuit), the second-stage current sources 633 connected to thefirst-stage current source are large in number, making it impossible toplace the first-stage current source 631 and third-stage current sources633 close to each other.

The source driver circuit 14 according to the present invention copiesthe current value of the first-stage current mirror circuit (currentsource 631) to the second-stage current mirror circuits (current sources632), and the current values of the second-stage current mirror circuits(current sources 632) to the third-stage current mirror circuits(current sources 632). With this configuration, the second-stage currentmirror circuits (current sources 632) connected to the first-stagecurrent mirror circuit (current source 631) are small in number. Thus,the first-stage current mirror circuit (current source 631) andsecond-stage current mirror circuits (current sources 632) can be placedclose to each other.

If transistors composing the current mirror circuits can be placed closeto each other, naturally variations in the transistors are reduced, andso are variations in current values. The number of the third-stagecurrent mirror circuits (current sources 633) connected to thesecond-stage current mirror circuits (current sources 632) are reducedas well. Consequently, the second-stage current mirror circuits (currentsources 632) and third-stage current mirror circuits (current sources633) can be placed close to each other.

That is, transistors in current receiving parts of the first-stagecurrent mirror circuit (current source 631), second-stage current mirrorcircuits (current sources 632), and third-stage current mirror circuits(current sources 633) can be placed close to each other on the whole. Inthis way, transistors composing the current mirror circuits can beplaced close to each other, reducing variations in the transistors andgreatly reducing variations in current signals from output terminals. Amulti-stage current mirror circuit consisting of three stages has beencited in the above example for the sake of simplicity. Needless to say,the larger the number of stages, the smaller the current variations inthe source driver IC 14 of the current-driven display panel. Thus, thenumber of stages of a current mirror circuit is not limited to three andmay be more than three.

In the present invention, the terms “current sources 631, 632, and 633”and “current mirror circuits” are used interchangeably. That is, currentsources are a basic construct of the present invention and the currentsources are embodied into current mirror circuits. Thus, a currentsource is not limited to a current mirror circuit and may be a currentcircuit consisting of a combination of a operational amplifier 722,transistor 631, and register R as shown in FIG. 72.

FIG. 64 is a structural drawing of a more concrete source driver IC(circuit) 14. It illustrates part of third current sources 633. This isan output part connected to one source signal line 18. It is composed ofmultiple current mirror circuits (current sources 634 (1 unit)) of thesame size as a current mirror configuration in the final stage. Theirnumber is bit-weighted according to the data size of image data.

Incidentally, the transistors composing the source driver IC (circuit)14 according to the present invention are not limited to a MOS type andmay be a bipolar type. Also, they are not limited to siliconsemiconductors and may be gallium arsenide semiconductors. Also, theymay be germanium semiconductors. Alternatively, they may be formeddirectly on a substrate using low-temperature polysilicon technology,other polysilicon technology, or amorphous silicon technology.

FIG. 48 illustrates an example of the present invention which handles6-bit digital input. Six bits are the sixth power of two, and thusprovide a 64-gradation display. This source driver IC 14, when mountedon an array board, provides 64 gradations each of red (R), green (G),and blue (B), meaning 64×64×64=approximately 260,000 colors.

Sixty-four (64) gradations require one D0-bit unit transistor 634, twoD1-bit unit transistors 634, four D2-bit unit transistors 634, eightD3-bit unit transistors 634, sixteen D4-bit unit transistors 634, andthirty-two D5-bit unit transistors 634 for a total of sixty-three unittransistors 634. Thus, the present invention produces one output usingas many unit transistors 634 as the number of gradations (64 gradationsin this example) minus 1. Incidentally, even if one unit transistor isdivided into a plurality of sub-unit transistors, this simply means thata unit transistor is divided into sub-unit transistors, and makes nodifference in the fact that the present invention uses as many unittransistors as the number of gradations minus 1.

In FIG. 64, D0 represents LSB input and D5 represents MSB input. When aD0 input terminal is high (positive logic), a switch 641 a is closed(the switch 481 a is an on/off means and may be constructed of a singletransistor or may be an analog switch consisting of a P-channeltransistor and N-channel transistor. Then, current flows to a currentsource (single-unit) 634 composing a current mirror. The current flowsthrough internal wiring 643 in the IC 14. Since the internal wiring 643is connected to the source signal line 18 via a terminal electrode ofthe IC 14, the current flowing through internal wiring 643 provides aprogramming current for the pixels 16.

For example, when a D1 input terminal is high (positive logic), a switch641 b is closed. Then, current flows to two current sources(single-unit) 634 composing a current mirror. The current flows throughthe internal wiring 643 in the IC 14. Since the internal wiring 643 isconnected to the source signal line 18 via a terminal electrode of theIC 14, the current flowing through internal wiring 643 provides aprogramming current for the pixels 16.

The same applies to the other switches 641. When a D2 input terminal ishigh (positive logic), a switch 641 c is closed. Then, current flows tofour current sources (single-unit) 634 composing a current mirror. Whena D5 input terminal is high (positive logic), a switch 641 f is closed.Then, current flows to 32 (thirty-two) current sources (single-unit) 634composing a current mirror.

In this way, based on external data (D0 to D5), current flows to thecorresponding current sources (single-unit). That is, current flows to 0to 63 current sources (single-unit) depending on the data.

Incidentally, for ease of explanation, it is assumed that there are 63current sources for a 6-bit configuration, but this is not restrictive.In the case of 8-bit configuration, 255 unit transistors 634 can beformed (placed). For a 4-bit configuration, 15 unit transistors 634 canbe formed (placed) The transistors 634 constituting the unit currentsources have a channel width W and channel width L. The use of equaltransistors makes it possible to construct output stages with smallvariations.

Besides, not all the current sources 634 need to pass equal current. Forexample, individual current sources 634 may be weighted. For example acurrent output circuit may be constructed using a mixture of single-unitcurrent sources 634, double-sized current sources 634, quadruple-sizedcurrent sources 634, etc. However, if current sources 634 are weighted,the weighted current sources may not provide the right proportions,resulting in variations. Thus, even when using weighting, it ispreferable to construct each current source from transistors each ofwhich corresponds to a single-unit current source.

The unit transistor 634 should be equal to or larger than a certainsize. The smaller the transistor size, the larger the variations inoutput current. The size of a transistor 634 is given by the channellength L multiplied by the channel width W. For example, if W=3 μm andL=4 μm, the size of the unit transistor 634 constituting a unit currentsource is W×L=12 square μm. It is believed that crystal boundaryconditions of silicon wafers have something to do with the fact that asmaller transistor size results in larger variations. Thus, variationsin output current of transistors are small when each transistor isformed across a plurality of crystal boundaries.

Relationship between size of transistors and variations in outputcurrent is shown in FIG. 117. The horizontal axis of the graph in FIG.117 represents transistor size (square μm). The vertical axis representsvariations in output current in percentage terms. The variations (%) inoutput current here were determined using groups of 63 unit currentsources (unit transistors) 634 formed on a wafer. Thus, although thehorizontal axis of the graph represents the size of a transistorconstituting one current source, since there are actually 63 transistorsconnected in parallel, the total area of the transistors is 63 timeslarger. However, the present invention is based on the size of a unittransistor 634. Thus, FIG. 117 shows that variations in the outputcurrent of 63 unit transistors 634 with an area of 30 square μm each is0.5%.

In the case of 64 gradations, 100/64=1.5%. Thus, the variations in theoutput current must be within 1.5%. From FIG. 117, it can been seen thatin order for the variations to be within 1.5%, the size of the unittransistor must be equal to or larger than 2 square μm (in the case of64 gradations, sixty-three 2-square μm unit transistors operate). On theother hand, there are limits to transistor size because largertransistors increase the size of an IC chip and there are limits to thewidth per one output. In this respect, the upper limit to the size ofthe unit transistor 634 is 300 square μm. Thus, in the case of 64gradations, the size of the unit transistor 634 must be from 2 square μmto 300 square μm (both inclusive).

In the case of 128 gradations, 100/128=1%. Thus, the variations in theoutput current must be within 1%. From FIG. 117, it can been seen thatin order for the variations to be within 1%, the size of the unittransistor must be equal to or larger than 8 square μm. Thus, in thecase of 128 gradations, the size of the unit transistor 634 must be from8 square μm to 300 square μm (both inclusive).

Generally, if the number of gradations is K and the size of a unittransistor 634 is St (square μm), the following relationship should besatisfied:40≦K/{square root}{square root over ( )}(St) and St≦300

More preferably, the following relationship should be satisfied:120≦K/f{square root}{square root over ( )}(St) and St≦300

In the above example 64 gradations are represented by 63 transistors.When representing 64 gradations by 127 unit transistors 634, theunit-transistor 634 size is the total size of two unit transistors 634.For example, in the case where 64 gradations are represented by 127 unittransistors 634, if the size of a unit transistor 484 is 10 square μm,the unit-transistor 484 size is given in FIG. 117 as 10×2=20. Similarly,in the case where 64 gradations are represented by 255 unit transistors634, if the size of a unit transistor 484 is 10 square μm, theunit-transistor size is given in FIG. 117 as 10×4=40.

It is necessary to take into consideration not only the size, but alsothe shape of the unit transistor 634. This is to reduce kink effect. Akink is a phenomenon in which current flowing through a unit transistor634 changes when the voltage between the source (S) and drain (D) of theunit transistor 634 is varied with the gate voltage of the unittransistor 634 kept constant. In the absence of kink effect (in idealstate), the current flowing through the unit transistor 634 does notchange even if the voltage applied between the source (S) and drain (D)of the unit transistor 484 is varied.

Kink effect occurs when the source signal lines 18 vary due tovariations in Vt of driver transistors 11 a shown in FIG. 1 and thelike. The driver circuit 14 passes programming current through thesource signal line 18 so that the programming current will flow throughthe driver transistor 11 a of the pixel. The programming current causeschanges in the gate terminal voltage of the driver transistor 11 a, andconsequently the programming current flows through the driver transistor11 a. As can be seen From FIG. 3, when a selected pixel 16 is inprogramming mode, the gate terminal voltage of the driver transistor 11a equals the potential of the source signal line 18.

Thus, the potentials of the source signal lines 18 vary due tovariations in Vt of the driver transistors 11 a in pixels 16. Thepotential of a source signal line 18 equals the source-drain voltage ofthe unit transistor 634 of the driver circuit 14. That is, variations inVt of the driver transistors 11 a in the pixels 16 cause thesource-drain voltage applied to the unit transistors 634 to vary. Then,the source-drain voltage causes variations in the output voltage of theunit transistor 634 due to kinks.

FIG. 118 is a graph which represents this phenomenon. The vertical axisrepresents the output current of the unit transistor 634 obtained when apredetermined voltage is applied to the gate terminal. The horizontalaxis represents the voltage between source (S) and drain (D). L in L/Wrepresents the channel length and W represents the channel width of theunit transistor 634. Also, L, W represents the size of the unittransistor 634 which outputs current for one gradation. Thus, to outputwith the current for one gradation using a plurality of sub-unittransistors, Wand L should be calculated by substituting the sub-unittransistors with an equivalent unit transistor 634. Basically, thecalculation should be performed by taking into consideration thetransistor size and output current.

When L/W equals 5/3, the output current remains almost unchanged even ifthe source-drain voltage rises. However, when L/W equals 1/1, the outputcurrent increases in approximate proportion to the source-drain voltage.Thus, the larger the L/W, the better.

FIG. 172 is a graph showing deviation (variation) in L/W of unittransistors from a target value. When the L/W ratio of unit transistorsis equal to smaller than 2, the deviation from the target value is large(the slope of the straight line is large). However, as L/W increases,the deviation from the target value tends to decrease. When L/W of unittransistors is equal to larger than 2, the deviation from the targetvalue is small. Also, the deviation from the target value is 0.5% orless when L/W=2 or more. Thus, this value can be used for source drivercircuits 14 to indicate accuracy of transistors.

In view of the above circumstances, it is preferable that L/W of a unittransistor is two or more.

However, a large L/W means a long L, and thus a large transistor size.

Thus, more preferably, L/W is 40 or less.

Besides, L/W also depends on the number of gradations. If the number ofgradations is small, there is no problem even if there are variations inthe output current of the unit transistor 634 due to kink effect becausethere are large differences between gradations. However, in the case ofa display panel with a large number of gradations, since there are smalldifferences between gradations, even small variations in the outputcurrent of the unit transistor 634 due to kink effect will decrease thenumber of gradations.

In view of the above circumstances, the driver circuit 14 according tothe present invention is configured to satisfy the followingrelationship:({square root}{square root over ( )}(K/16))≦L/W≦ and ({squareroot}{square root over ( )}(K/16))×20where K is the number of gradations, L is the channel length of the unittransistor 634, and W is the channel width of the unit transistor. Thisrelationship is illustrated in FIG. 119. The area above the straightline in FIG. 119 is relevant to the present invention.

This corresponds to the third-stage current mirror portion illustratedin FIG. 63. Thus, a first current source 631 and second current sources632 are formed separately and are placed densely (close to each other).Besides, the transistors 633 a in the current mirror circuits composingthe second current sources 632 and third current sources are also placeddensely (close to each other).

The variations in the output current of the unit transistor 634 alsodepend on the voltage resistance of the source driver IC 14. The voltageresistance of the source driver IC generally means the power supplyvoltage of the IC. For example, voltage resistance of 5 V means the useof the power supply voltage at a standard voltage of 5 V. Incidentally,IC voltage resistance can translate into maximum working voltage.Semiconductor IC makers have standardized voltage-resistance processessuch as a 5-V voltage-resistance process and 10-V voltage-resistanceprocess.

It is believed that film properties and film thickness of a gateinsulating film of the unit transistor 634 have something to do with thefact that IC voltage resistance affects variations in the output currentof the unit transistor 634. The transistors 634 produced in a processwith high IC voltage resistance have a thick gate insulating film. Thisis intended to avoid dielectric breakdown even under application of ahigh voltage. A thick gate insulating film makes its control difficultand increases variations in its film properties. This increasesvariations in the transistors. Also, the transistors produced in a highvoltage-resistance process have low mobility. With low mobility, evenslight changes in electrons injected into transistor gates cause changesin characteristics. This increases variations in the transistors. Toreduce variations in the unit transistors 634, it is preferable to adoptan IC process with low IC voltage resistance.

FIG. 170 illustrates relationship between IC voltage resistance andoutput variations of unit transistors. The variation rate on thevertical axis is based on the variation of unit transistors 634 producedin a 1.8-V voltage resistance process, which variation is taken to be 1.FIG. 170 shows output variations of unit transistors 634 which wereproduced in various IC voltage resistance processes and have a shape ofL/W=12/6 (μm). A plurality of unit transistors 634 were produced in eachIC voltage resistance process and variations in their output currentwere determined. The voltage resistance processes were composeddiscretely of 1.8-V voltage resistance, 2.5-V voltage resistance, 3.3-Vvoltage resistance, 5-V voltage resistance, 8-V voltage resistance, and10-V voltage resistance, 15-V voltage resistance processes. However, forease of explanation, variations in the transistors formed in thedifferent voltage resistance processes are plotted on the graph andconnected with straight lines.

As can be seen from FIG. 170, the variation rate (variations in theoutput current of the unit transistors 634) increases gradually up untilan IC voltage resistance of 9 V. However, when the IC voltage resistanceexceeds 10 V, the slope of the variation rate with respect to the ICvoltage resistance becomes large.

In FIG. 170, the permissible limit to the variation rate is 3 for 64- to256-gradation display. The variation rate varies with the area, L/W,etc. of the unit transistor 634. However, the variation rate withrespect to the IC voltage resistance is hardly affected by the shape ofthe unit transistor 634. The variation rate tends to increase above anIC voltage resistance of 9 to 10 V.

On the other hand, the potential at an output terminal 64 in FIG. 64varies with the programming current in the driver transistor 11 a of thepixel 16. When the driver transistor 11 a of the pixel 16 passes whiteraster (maximum white display) current, its gate terminal voltage isdesignated as Vw. When the driver transistor 11 a of the pixel 16 passesblack raster (completely black display) current, its gate terminalvoltage is designated as Vb. The absolute value of Vw-Vb must be 2 V orlarger. When the voltage Vw is applied to the output terminal 761,inter-channel voltage of the unit transistor 634 must be 0.5 V orhigher.

Thus, a voltage of 0.5 V to ((Vw−Vb)+0.5) V is applied to the terminal761 (during current programming, the gate terminal voltage of the drivertransistor 11 a of the pixel 16 is applied to the output terminal 761,which is connected with the source signal line 18). Since Vw−Vb equals 2V, a voltage of up to 2 V+0.5 V=2.5 V is applied to the output terminal761. Thus, even if the output voltage (current) of the source driver IC14 is based on a rail-to-rail output, the IC voltage resistance must be2.5V. The amplitude required by a terminal 741 is 2.5 V or more.

Thus, it is preferable to use a voltage resistance process in the rangeof 2.5-V to 10-V (both inclusive) for the source driver IC 14. Morepreferably, a voltage resistance process in the range of 3-V to 9-V(both inclusive) is used for the source driver IC 14.

Incidentally, it has been described that a voltage resistance process inthe range of 2.5-V to 10-V (both inclusive) is used for the sourcedriver IC 12. This voltage resistance is also applied to examples (e.g.,a low-temperature polysilicon process) in which the source drivercircuit 14 is formed directly on an array board 71. Working voltageresistance of a source driver circuit 14 formed directly on an arrayboard 71 can be high and exceeds 15 V in some cases. In such cases, thepower supply voltage used for the source driver circuit 14 may besubstituted with the IC voltage resistance illustrated in FIG. 170.Also, the source driver IC 14 may have the IC voltage resistancesubstituted with the power supply voltage used.

The area of a unit transistor 634 is correlated with the variations inits output current. FIG. 171 is a graph obtained by varying thetransistor width W of a unit transistor 634 with the area of the unittransistor 634 kept constant. In FIG. 170, the variation of the unittransistor 634 with a channel width W of 2 μm is taken as 1. As can beseen from FIG. 171 the variation rate increases gradually when W of theunit transistor is from 2 μm to 9 or 10 μm. The increase in thevariation rate tends to become large when W is 10 μm or more. Also, thevariation rate tends to increase when the channel width W=2 μm or less.

In FIG. 171, the permissible limit to the variation rate is 3 for 64- to256-gradation display. The variation rate varies with the area of theunit transistor 634. However, the variation rate with respect to the ICvoltage resistance is hardly affected by the area of the unit transistor634.

Thus, preferably, the channel width W of the unit transistor 634 is from2 μm to 10 μm (both inclusive). More preferably, the channel width W ofthe unit transistor 634 is from 2 μm to 9 μm (both inclusive).

As illustrated in FIG. 68, current flowing through second-stage currentmirror circuits 632 b is copied to transistors 633 a which composethird-stage current mirror circuits. If a current mirror ratio is 1, thecurrent flows through transistors 633 b. The current is copied to theunit transistor 634 in the final stage.

D0, which is provided by one unit transistor 634, provides the value ofthe current flowing through the unit transistor 633 of the final-stagecurrent source. D1, which is provided by two unit transistors 634,provides a two times larger current value than the final-stage currentsource. D2, which is provided by four unit transistors 634, provides afour times larger current value than the final-stage current source; andD5, which is provided by 32 unit transistors 484, provides a 32 timeslarger current value than the final-stage current source.

Accordingly, programming current Iw is output (drawn) to the sourcesignal line via switches controlled by 6-bit image data consisting ofD0, D1, D2, . . . , and D5. Thus, according to activation anddeactivation of the 6-bit image data consisting of D0, D1, D2, . . . ,and D5, currents 1 time, 2 times, 4 times, . . . and/or 32 times aslarge as the final-stage current source 633 are added and outputted tothe output line. That is, according to activation and deactivation ofthe 6-bit image data consisting of D0, D1, D2, . . . , and D5, 0 to 63times as large a current as the final-stage current source 633 is outputfrom the output line (the current is drawn from the source signal line18).

Actually, as illustrated in FIG. 146, in the source driver IC 14,reference currents (IaR, IaG, and IaB) for R, G, and B, respectively,can be adjusted by variable resistors 651 (651R, 651G, and 651B). Byadjusting the reference currents Ia, the white balance can be adjustedeasily.

The use of integral multiples of the current values of the final-stagecurrent sources 633 thus makes it possible to control current valuesmore accurately (reduce output variations among terminals) thanconventional methods which use W/L-based proportional allotments.

However, this configuration is available only when the drivertransistors 11 a of pixels 16 are P-channel transistors and the currentsources (single-unit transistors) 634 of the source driver IC 14 areN-channel transistors.

In other cases (e.g., when the driver transistors 11 a of pixels 16 areN-channel transistors), the present invention can use a configuration inwhich the programming current Iw is a discharge current.

Now, a reference current generator circuit will be described in detail.Current output mode used for the source driver circuit (IC) 14 of thepresent invention uses a reference current and outputs the programmingcurrent Iw by combining unit currents which are proportional to areference current (source drivers of liquid crystal display panels usevoltage output mode, which uses steps of voltage as signals). FIG. 144shows an example. In FIGS. 67, 68, 76, etc. a variable resistor 651 isused to generate reference current. In FIG. 144, the variable resistor651 in FIG. 68 is replaced by the transistor 631 a and current flowingthrough a transistor 1444 which forms a current mirror circuit inconjunction with the transistor 631 a is controlled by an operationalamplifier 722 or the like. The transistor 1444 and transistor 631 aforms the current mirror circuit. If the current mirror factor is 1, thecurrent flowing through the transistor 1444 provides a referencecurrent.

Output voltage of the operational amplifier 722 is fed to an N-channeltransistor 1443 and the current flowing through the N-channel transistor1443 flows through an external resistor 691. Incidentally, a resistor691 a is a fixed-chip resister. Basically, the resistor 691 a is enough.A resistor 691 b is a resistive element such as a posistor or thermistorwhose value changes with temperature.

The resistor 691 a is used to compensate for temperature characteristicsof the EL element 15. The resistor 691 a is inserted or placed inparallel or series with the resistor 691 b according to (to compensatefor) the temperature characteristics of the EL element 15. Incidentally,for ease of explanation, the resistor 691 a and resistor 691 b will betreated below as one resistor 691.

A resistor 691 with an accuracy of 1% or better is easily available. Theresistor 691 may be built into the source driver IC 14 using diffusedresistor technology or a polysilicon pattern. The chip resistor 691 ismounted on an input terminal 761 a. In the case of EL display panels, inparticular, the temperature characteristics of EL elements 15 differamong R, G, and B. Thus, three external resistors 691 are required forR, G, and B.

Terminal voltage of the resistor 691 provides a negative input to theoperational amplifier 722 and the voltage at the negative terminal hasthe same magnitude as the voltage at a positive terminal of theoperational amplifier 722. Thus, if a positive input voltage of theoperational amplifier 722 is V1, the current obtained by dividing withthis voltage by the resistance 691 flows through the transistor 1444.This current serves as the reference current. If the resistance of theresistor 691 is 100 KΩ and the input voltage of the positive terminal ofthe operational amplifier 722 is V1=1 (V), a reference current of 10(μA) (=1 (V)/100 KΩ) flows through the resistor 691. Preferably, thereference current is set between 2 μA and 30 μA (both inclusive). Morepreferably, it is set between 5 μA and 20 μA (both inclusive) A smallreference current flowing through the parent transistor 63 lowers theaccuracy of the unit current source 634. Too large a reference currentincreases the current mirror factor converted (in the downward directionin this case) within the IC, increasing variations in the current mirrorcircuit, and thus lowering the accuracy of the unit current source 634again.

The above configuration makes it possible to form an extremely accuratereference current (in terms of size and variations) provided that thepositive input terminal of the operational amplifier 722 and theresistor 691 are accurate enough. When building the resistor 691 intothe source driver circuit (IC) 14, it is recommended to trim theincorporated resistor to increase accuracy.

A reference voltage Vref received from a reference voltage circuit 1441is applied to the positive terminal of the operational amplifier 722.Regarding ICs for the reference voltage circuit 1441 which outputs thereference voltage, various types are available from Maxim and othercompanies. Alternatively, the reference voltage Vref may be generatedwithin the source driver circuit 14 (internally generated referencevoltage Vref). Preferably, the reference voltage Vref ranges between 2(V) and the anode voltage Vdd (V) (both inclusive).

The reference voltage is fed through a connection terminal 761 a.Basically, the voltage Vref can be fed into the positive terminal of theoperational amplifier 722. An electronic regulator circuit 561 is placedbetween the connection terminal 761 a and positive terminal because theluminous efficiency of the EL elements 15 varies among R, G, and B. Inother words, the electronic regulator circuit 561 is intended to adjustthe current passed through each of the EL elements 15 for R, G, and B,and thereby achieve a white balance. Of course, what can be adjusted bythe resistor 691 does not need to be adjusted by the electronicregulator circuit 561. For example, a variable resistor may be used asthe resistor 691. One of the uses of the electronic regulator circuit561 is to readjust white balance when the degradation rate of the ELelements 15 varies among R, G, and B. The EL elements 15 for B areespecially prone to degradation. Thus, the EL elements 15 for B becomedarker with years of use of a EL display panel, turning the screenyellowish. In that case, the white balance is adjusted using theelectronic regulator circuit 561 for B. Of course, brightness correctionor white balance correction of the EL elements may be performed bylinking the electronic regulator circuit 561 to a temperature sensor 781(see FIG. 78 and its description).

The electronic regulator circuit 561 is built into the IC (circuit) 14.Alternatively, it is formed directly on an array board 71 using thelow-temperature poly-silicon technology. A plurality of unit resistors(R1, R2, R3, R4, . . . Rn) formed through polysilicon patterning areconnected in series. Analog switches (S1, S2, S2, . . . Sn+1) are placedamong the unit resistors, the reference voltage Vref is divided, and theresulting voltages are output.

In FIG. 148 and the like, the transistor 1443 is illustrated as abipolar transistor, but this is not restrictive. It may be a FET or MOStransistor. Needless to say, there is no need to built the transistor1443 into the IC 14, and may be placed outside the IC. Also, powergenerator and other generator circuits as well as the transistor 1443may be built into the gate driver circuit 12.

In order to achieve full-color display on an EL display panel, it isnecessary to provide a reference current for each of R, G, and B. Thewhite balance can be adjusted by controlling the ratios of the RGBreference currents. In the case of current driving as well as thepresent invention, the value of current passed by the unit currentsource 634 is determined based on one reference current. Thus, thecurrent passed by the unit current source 634 can be determined bydetermining the magnitude of the reference current. Consequently, thewhite balance in every gradation can be achieved by setting a referencecurrent for each of R, G, and B. The above matters work because thesource driver circuit 14 produces current outputs varied in steps (iscurrent-driven). Thus, the point is how the magnitude of the referencecurrent can be set for each of R, G, and B.

The light emission efficiency of an EL element is determined by, ordepends heavily on, the thickness of a film vapor-deposited or appliedto the EL element. The film thickness is almost constant within eachlot. Through lot control of the film thickness of the EL element 15, itis possible to determine relationship between the current passed throughthe EL element 15 and light emission efficiency. That is, the currentvalue used for white balancing is fixed for each lot.

For example, if the currents passed through the EL elements 15 for R, G,and B are Ir (A), Ig (A), and Ib (A), respectively, a ratio of referencecurrents which can achieve a white balance can be known on a lot-by-lotbasis.

Therefore, a white balance can be achieved, for example, whenIr:Ig:Ib=1:2:4. With the duty ratio driving, etc. according to thepresent invention, once a white balance is achieved, it is applied toall gradations. This is accomplished by synergy between a drive methodaccording to the present invention and source driver circuit accordingto the present invention.

With the configuration shown in FIG. 148, the values of the resistors691 in the circuits which generate RGB reference currents can be changedon a lot-by-lot basis to achieve a white balance. However, the resistors691 must be changed on a lot-by-lot basis.

In FIG. 148, the electronic regulator circuit 561 is controlled from theoutside of the source driver circuit (IC) 14 and the value of thereference current Ia is changed by operating switches Sx in theelectronic regulator circuit 561. In FIG. 149, settings of theelectronic regulator circuits 561 can be stored in flash memories 1491.Values in the flash memories 1491 can be set by the RGB electronicregulator circuits 561 independently of one another. The values in theflash memories 1491 are set, for example, for each lot of EL displaypanels and read out upon power-up of the source driver IC 14 to set theswitches Sx in the electronic regulator circuits 561.

FIG. 150 is a block diagram in which the electronic regulator circuit561 in FIG. 149 is configured as a resistor array circuit 1501. In FIG.150, reference character Rr denotes an external resistor. Of course, Rrmay be built into the source driver circuit (IC) 14. Resistor arrays1503 are built into the source driver circuit (IC) 14. Resistors (R1 toRn) composing the resistor array are connected in series and theresistors (R1 to Rn) are connected by short-circuiting wires. Cuttingthis connection at point a or b, etc. shown in FIG. 150 varies thecurrent Ir flowing through the resistor array 1503. Changes in thecurrent Ir cause changes to the voltage applied to the positive terminalof the operational amplifier 722, resulting in changes in the referencecurrent Ia. The point at which the connection will be cut is determinedby monitoring the current flowing through the resistor Rr, in such a wayas to produce a target reference current.

To trim the resistor array 1503, laser light 1502 can be emitted from alaser device 1501.

Incidentally it has been stated with reference to FIG. 148 that the RGBreference currents are varied by varying the values of RGB resistors691. Also, it has been stated with reference to FIG. 149 that the RGBreference currents are varied by operating the switches Sx in theelectronic regulator circuits 561 using values stored in the flashmemories 1491. Also, it has been stated with reference to FIG. 150 thatthe RGB reference currents are varied by trimming the resistance valuesof the resistor array 1503. However, the present invention is notlimited to that.

For example, needless to say, the reference currents can be varied byvarying the value of each of RGB reference voltages (VrefR, VrefG, andVrefB) in FIGS. 149 and 150. The RGB reference voltages Vref can begenerated easily by an operational amplifier circuit or the like. Also,in FIGS. 148, 149, 150, etc., by using the resistor Rr as a regulator,it is possible to vary the reference voltage applied to the sourcedriver circuit (IC) 14, as a result.

It has been stated that 0 to 63 times the current of the final-stagecurrent sources 633 is outputted, but this is true only when the currentmirror factor of the final-stage current sources 633 is 1. When thecurrent mirror factor is 2, 0 to 126 times the current of thefinal-stage current sources 633 is output and when the current mirrorfactor is 0.5, 0 to 31.5 times the current of the final-stage currentsources 633 is output.

Thus, the present invention allows the values of output current to bechanged easily by changing the current mirror factor of the final-stagecurrent sources 633 or current sources (631, 632, etc.) in precedingstages. Preferably, the current mirror factor is varied (differed)separately for R, G, and B. The current mirror factor of any currentsource only for R, for example, may be varied (differed) from the othercolors (from the current source circuits for the other colors). ELdisplay panels, in particular, have different luminous efficiencies fordifferent colors (R, G, and B; or cyan, yellow, and magenta). Thus, byvarying the current mirror factor among different colors, it is possibleto improve the white balance.

The current mirror factor of current sources may be varied (differed)from the other colors (from the current source circuits for the othercolors) in an unfixed manner. It may be variable. The current mirrorfactor can be made variable by providing a plurality of transistorscomposing a current mirror circuit in a current source and changing,based on external signals, the number of transistors through whichcurrent current is passed. This configuration makes it possible toachieve an optimum white balance through adjustments while observingemission condition of manufactured EL display panels in various colors.

The present invention in particular is configured to connect currentsources (current mirror circuits) in multiple stages. Thus, by varyingthe current mirror factor between the first-stage current source 631 andsecond-stage current sources 632, it is possible to vary the outputcurrents of a large number of outputs easily using a small number ofconnections (current mirror circuits and the like). Needless to say,this makes it possible to vary the output currents of a large number ofoutputs easily using a smaller number of connections (current mirrorcircuits and the like) than by varying the current mirror factor betweenthe second-stage current sources 632 and third-stage current sources633.

Incidentally, varying a current mirror factor means varying (adjusting)a magnification factor of current. Thus, it is not limited to currentmirror circuits. For example, it can be implemented by an operationalamplifier circuit for current output or a D/A circuit for currentoutput. The items described above also apply to other examples of thepresent invention.

FIG. 65 is an exemplary circuit diagram showing 176 outputs (N×M=176) ofa three-stage current mirror circuit. In FIG. 65, the current source 631constituted of the first-stage current mirror circuit is referred to asa parent current source, the current sources 632 constituted of thesecond-stage current mirror circuits are referred to as child currentsources, and the current sources 633 constituted of the third-stagecurrent mirror circuits are referred to as grandchild current sources.The use of an integral multiple for the third-stage current mirrorcircuits which are the final-stage current mirror circuits makes itpossible to minimize variations in the 176 outputs and producehigh-accuracy current outputs. Of course, it should be remembered thatthe current sources 531, 632, and 633 must be placed densely.

Incidentally, dense placement means placing the first current source 631and the second current sources 632 (the current or voltage output andcurrent or voltage input) at least within a distance of 8 mm. Morepreferably, they are placed within 5 mm. It has been shown analyticallythat when placed at this density, the current sources can fit into asilicon chip with little difference in transistor characteristics (Vtand mobility (μ)) Similarly, the second current sources 632 and thirdcurrent sources 633 (the current output and current input) are placed atleast within a distance of 8 mm. More preferably, they are placed within5 mm. Needless to say, the above items also apply to other examples ofthe present invention.

The current or voltage output and current or voltage input mean thefollowing relationships. In the case of voltage-based delivery shown inFIG. 66, the transistor 631 (the output) of the (I)-th current sourceand the transistor 632 a (the input) of the (I+1)-th current source areplaced close to each other. In the case of current-based delivery shownin FIG. 67, the transistor 631 a (the output) of the (I)-th currentsource and the transistor 632 b (the input) of the (I+1)-th currentsource are placed close to each other.

Incidentally, although it is assumed in FIGS. 65, 66, etc. that there isone transistor 631, this is not restrictive. For example, it is alsopossible to form a plurality of small sub-transistors 631 and connectthe source or drain terminals of the sub-transistors with the variableresistor 651 to form a unit transistor. By connecting the plurality ofsmall sub-transistors in parallel, it is possible to reduce variationsof the unit transistor.

Similarly, although it is assumed that there is one transistor 632 a,this is not restrictive. For example, it is also possible to form aplurality of small sub-transistors 632 a and connect the gate terminalsof the transistors 632 a with the gate terminal of the transistor 631.By connecting the plurality of small transistors 632 a in parallel, itis possible to reduce variations of the transistor 632 a.

Thus, according to the present invention, the following configurationscan be illustrated: a configuration in which one transistor 631 isconnected with a plurality of transistors 632 a, a configuration inwhich a plurality of transistors 631 are connected with one transistor632 a, and a configuration in which a plurality of transistors 631 areconnected with a plurality of transistors 632 a. These examples will bedescribed in more detail below.

The above items also apply to a configuration of transistors 633 a and633 b in FIG. 68. Possible configurations include a configuration inwhich one transistor 633 a is connected with a plurality of transistors633 b, a configuration in which a plurality of transistors 633 a areconnected with one transistor 633 b, and a configuration in which aplurality of transistors 633 a are connected with a plurality oftransistors 633 b. By connecting the plurality of small transistors 633in parallel, it is possible to reduce variations of the transistor 633.

The above items also apply to relationship between transistors 632 a and632 b in FIG. 68. Also, preferably a plurality of transistors 633 b areused in FIG. 64. Similarly, it is preferable to use plurality oftransistors 633 in FIGS. 73 and 74.

Although description is made as a silicon chip here, this means asemiconductor chip. Thus, the chip as referred to here may be a chipformed on a gallium substrate or other semiconductor chip formed on agermanium substrate or the like. Thus, the source driver IC 14 may beconstructed of any semiconductor substrate. Also, the unit transistor634 may be a bipolar transistor, CMOS transistor, Bi-CMOS transistor, orDMOS transistor. However, in terms of reducing variations in the outputof the unit transistor 634, preferably a CMOS transistor is used for theunit transistor 634.

Preferably, the unit transistor 634 is an N-channel transistor. The unittransistor consisting of a P-channel transistor has 1.5 times largeroutput variations than the unit transistor consisting of an N-channeltransistor.

Since it is preferable that the unit transistor 634 of the source driverIC 14 is an N-channel transistor, the programming current of the sourcedriver IC 14 is a current drawn from the pixel 16. Thus, the drivertransistor 11 a of the pixel 16 is a P-channel transistor. The switchingtransistor 11 d in FIG. 1 is also a P-channel transistor.

Thus, the configuration in which the unit transistor 634 in the outputstage of the source driver IC (circuit) 14 is an N-channel transistorand the driver transistor 11 a of the pixel 16 is a P-channel transistoris characteristic of the present invention. Incidentally, if all thetransistors 11 composing the pixel 16 are illustrated in FIG. 1, this ismore preferable because this can reduce the number of process masksrequired to produce the pixel 16.

If P-channel transistors are used as the transistors 11 of pixels 16,programming current flows in the direction from the pixels 16 to thesource signal lines 18. Thus, N-channel transistors should be used forthe unit transistors 634 (see FIGS. 73, 74, 126, and 129) of the sourcedriver circuit. That is, the source driver circuit 14 should beconfigured in such a way as to draw the programming current Iw.

Thus, if the driver transistors 11 a of the pixels 16 (in the case ofFIG. 1) are P-channel transistors, the unit transistors 634 of thesource driver circuit 14 must always be N-channel transistors to ensurethat the source driver circuit 14 will draw the programming current Iw.In order to form a source driver circuit 14 on an array board 71, it isnecessary to use both masks (processes) for N-channel transistors andmasks (processes) for P-channel transistors. Conceptually speaking, inthe display panel (display apparatus) of the present invention,P-channel transistors are used for the pixels 16 and gate drivercircuits 12 while N-channel transistors are used as the transistors ofdrawing current sources of the source drivers.

Thus, P-channel transistors are used as the transistors 11 of pixels 16and for the gate driver circuits 12. This makes it possible to reducethe costs of the array boards 71. However, in the source driver 14, unittransistors 634 must be N-channel transistors. Thus, the source drivercircuit 14 cannot be formed directly on a board 71. Thus, the sourcedriver circuit 14 is made of a silicon chip and the like separately andmounted on the array board 71. In short, the present invention isconfigured to mount the source driver IC 14 (means of outputtingprogramming current as video signals) externally.

Incidentally, although it has been stated that the source driver circuit14 is made of a silicon chip, this is not restrictive. For example, alarge number of source driver circuits may be formed on a glasssubstrate simultaneously using low-temperature polysilicon technology orthe like, cut off into chips, and mounted on boards 71. Incidentally,although it has been stated that a source driver circuit is mounted on aboard 71, this is not restrictive. Any form may be adopted as long asthe output terminals 681 of the source driver circuit 14 are connectedto the source signal lines 18 of the board 71. For example, the sourcedriver circuit 14 may be connected to the source signal lines 18 usingTAB technology. By forming a source driver circuit 14 on a silicon chipand the like separately, it is possible to reduce variations in outputcurrent and achieve proper image display as well as to reduce costs.

The configuration in which P-channel transistors are used as selectiontransistors of pixels 16 and for gate driver circuits is not limited toorganic EL or other self-luminous devices (display panels or displayapparatus). For example, it is also applicable to liquid crystal displaydevice and FEDs (field emission displays).

If the switching transistors 11 b and 11 c of a pixel 16 are P-channeltransistors, the pixel 16 becomes selected at Vgh, and becomesdeselected at Vgl. As described earlier, when the gate signal line 17 achanges from Vgl (on) to Vgh (off), voltage penetrates (penetrationvoltage). If the driver transistor 11 a of the pixel 16 is a P-channeltransistor, the penetration voltage more tightly restricts the flow ofcurrent through the transistor 11 a in black display mode. This makes itpossible to achieve a proper black display. The problem with thecurrent-driven system is that it is difficult to achieve a blackdisplay.

According to the present invention, because P-channel transistors areused for the gate driver circuits 12, the turn-on voltage corresponds toVgh. Thus, the gate driver circuits 12 match well with the pixels 16constructed from P-channel transistors. Also, to improve black display,it is important that the programming current Iw flows from the anodevoltage Vdd to the unit transistors 634 of the source driver circuit 14via the driver transistors 11 a and source signal lines 18, as is thecase with the pixel 16 configuration shown in FIGS. 1, 2, 32, 140, 142,144, and 145. Thus, a good synergistic effect can be produced ifP-channel transistors are used for the gate driver circuits 12 andpixels 16, the source driver circuit 14 is mounted on the substrate, andN-channel transistors are used as the unit transistors 634 of the sourcedriver circuit 14. Besides, unit transistors 634 constituted ofN-channel transistors have smaller variations in output current thanunit transistors 634 constituted of P-channel transistors. N-channelunit transistors 634 have 1/1.5 to 1/2 as large variations in outputcurrent as P-channel unit transistors 634 when they have the same area(W*L). For this reason, it is preferable that N-channel transistors areused as the unit transistors 634 of the source driver IC 14.

The same applies to FIG. 42(b). FIG. 42(b) shows a configuration inwhich a programming current Iw flows from an anode voltage Vdd to theunit transistors 634 of a source driver circuit 14 via a programmingtransistor 11 a and source signal line 18 rather than a configuration inwhich current flows into the unit transistors 634 of a source drivercircuit 14 via a driver transistor 11 b. Thus, as in the case of FIG. 1,a good synergistic effect can be produced if P-channel transistors areused for the gate driver circuits 12 and pixels 16, the source drivercircuit 14 is mounted on the substrate, and N-channel transistors areused as the unit transistors 634 of the source driver circuit 14.

According to the present invention, the driver transistors 11 a of thepixels 16 are P-channel transistors and the switching transistors 11 band 11 c are P-channel transistors. Also, the unit transistors 634 inthe output stages of the source driver IC 14 are N-channel transistors.Besides, preferably P-channel transistors are used for the gate drivercircuits 12.

Needless to say, a configuration in which P-channel and N-channeltransistors are interchanged also works well. Specifically, the drivertransistors 11 a of the pixels 16 are N-channel transistors and theswitching transistors 11 b and 11 c are N-channel transistors. Also, theunit transistors 634 in the output stages of the source driver IC 14 areP-channel transistors. Besides, preferably N-channel transistors areused for the gate driver circuits 12. This configuration also belongs tothe present invention.

The above items apply not only to an IC which contain a single unittransistor 634, but also to a source driver IC 14 with anotherconfiguration such as a source driver circuit whose current output stagecontains a plurality of transistors or current mirrors.

Besides, they also apply to source driver circuits 14 by usingsemiconductor films of low-temperature polysilicon, high-temperaturepolysilicon, CGS formed by solid-phase growth, or amorphous silicon. Inthat case, however, panels are often relatively large. On a large panel,it is hard to visually perceive the effect of some variations in theoutput from the source signal lines 18.

Thus, in the case of a display panel in which a source driver circuit 14is formed on the glass substrate or the like together with pixeltransistors, dense placement means placing the first current source 631and second current sources 632 (the input and output of current) atleast within 30 mm (inclusive) of each other. More preferably, they arewithin 20 mm (inclusive) of each other. It has been shown analyticallythat there is little difference in characteristics (Vt and mobility (μ))of transistors placed in this range. Similarly, the second currentsources 632 and third current sources 633 (the input and output ofcurrent) are placed at least within 30 mm (inclusive) of each other.More preferably, they are within 20 mm (inclusive) of each other.

It has been stated for ease of understanding and explanation thatsignals are transferred between current mirror circuits by way ofvoltage. However, by using current-based delivery. It is possible toreduce variations in the driver circuit (IC) 14 of a current-drivendisplay panel.

FIG. 67 shows an example of configuration for current-based delivery.FIG. 66 also shows an example of configuration for current-baseddelivery. FIGS. 66 and 67 are similar in terms of circuit diagrams anddiffer in layout configuration, i.e., wiring layout. In FIG. 66,reference numeral 631 denotes an N-channel transistor for thefirst-stage current source, 632 a denotes an N-channel transistor for asecond-stage current source, and 632 b denotes a P-channel transistorfor a second-stage current source.

In FIG. 67, reference numeral 631 a denotes a first-stage N-channelcurrent source transistor, 632 a denotes a second-stage N-channelcurrent source transistor, and 632 b denotes a second-stage P-channelcurrent source transistor.

In FIG. 66, the gate voltage of the first-stage current sourceconsisting of a variable register 651 (used to vary current) and theN-channel transistor 631 is delivered to the gate of the N-channeltransistor 632 a of the second-stage current source. Thus, this is alayout configuration of a voltage-based delivery type.

In FIG. 67, the gate voltage of the first-stage current sourceconsisting of a variable register 651 and the N-channel transistor 631 ais applied to the gate of the N-channel transistor 632 a of the adjacentsecond-stage current source, and consequently the value of the currentflowing through the transistor is delivered to the P-channel transistor632 b of the second-stage current source. Thus, this is a layoutconfiguration of a current-based delivery type.

Incidentally, although this example of the present invention focuses onrelationship between the first current source and second current sourcefor ease of explanation or understanding, this is not restrictive and itgoes without saying that this example also applies (can be applied) torelationship between the second current source and third current sourceas well as relationship between other current sources.

In the layout configuration of the current mirror circuit of thevoltage-based delivery type shown in FIG. 66, the N-channel transistor631 of the first-stage current source and the N-channel transistor 632 aof the second-stage current source composing the current mirror circuitare separated (or liable to get separated, to be precise), and thus thetwo transistors tend to differ in characteristics. Consequently, thecurrent value of the first-stage current source is not transmittedcorrectly to the second-stage current source and there can bevariations.

In contrast, in the layout configuration of the current mirror circuitof the current-based delivery type shown in FIG. 67, the N-channeltransistor 631 a of the first-stage current source and the N-channeltransistor 632 a of the second-stage current source composing thecurrent mirror circuit are located adjacent to each other (easy to placeadjacent to each other), and thus the two transistors hardly differ incharacteristics. Consequently, the current value of the first-stagecurrent source is transmitted correctly to the second-stage currentsource and there can be little variations.

In view of the above circumstances, it is preferable to use a layoutconfiguration of the current-based delivery type instead of thevoltage-based delivery type for the circuit configuration of themulti-stage current mirror circuit according to the present invention(the source driver IC (circuit) 14 of the current-based delivery typeaccording to the present invention) in terms of reduced variations.Needless to say the above example can be applied to other examples ofthe present invention.

Incidentally, although delivery from the first-stage current source tothe second-stage current source has been cited for the sake ofexplanation, the same applies to delivery from the second-stage currentsource to the third-stage current source, delivery from the third-stagecurrent source to the fourth-stage current source, and so on.

FIG. 68 shows a current-based delivery version of three-stage currentmirror circuit (three-stage current source) shown in FIG. 65 (which,therefore shows a circuit configuration of a voltage-based deliverytype).

In FIG. 68, a reference current is created first by the variableregister 651 and N-channel transistor 631. Incidentally, although it isstated that the reference current is adjusted by the variable register651, actually the source voltage of the transistor 631 is set andregulated by an electronic regulator formed (or placed) in the sourcedriver IC (circuit) 14. Alternatively, the reference current is adjustedby directly supplying the source terminal of the transistor 631 withcurrent outputted from a current-type electronic regulator consisting ofa large number of unit transistors (single-unit) 634 as shown in FIG. 64(see FIG. 69).

The gate voltage of the first-stage current source constituted of thetransistor 631 is applied to the gate of the N-channel transistor 632 aof the adjacent second-stage current source, and the currentconsequently flowing through the transistor is delivered to theP-channel transistor 632 b of the second-stage current source. Also, thegate voltage of the P-channel transistor 632 b of the second-stagecurrent source is applied to the gate of the N-channel transistor 633 aof the adjacent third-stage current source, and the current consequentlyflowing through the transistor is delivered to the N-channel transistor633 b of the third-stage current source. A large number of currentsources 634 are formed (placed) at the gate of the N-channel transistor633 b of the third-stage current source according to the required bitcount as illustrated in FIG. 64.

The configuration in FIG. 69 is characterized in that the first-stagecurrent source 631 of the multi-stage current mirror circuit is equippedwith a current-value adjustment element. This configuration allowsoutput current to be controlled by varying the current value of thefirst-stage current source 631.

Variations in the Vt of transistors (variations in characteristics) areon the order of 100 mV within a wafer. However, variations in Vt oftransistors formed within 100 μ of each other should be 10 mV or less(actual measurement) That is, by configuring a current mirror circuitwith transistors formed close to each other, it is possible to reducevariations in the output current of the current mirror circuit. Thisreduces variations in the output current among terminals of the sourcedriver IC.

Incidentally, although variations in Vt are described as variationsamong transistors, variations among transistors are not limited tovariations in Vt. However, since variations in Vt are a main cause ofvariations among transistors, it is assumed that the variations inVt=the variations among transistors, for ease of understanding.

FIG. 110 shows formation areas of transistors (square millimeter) versusvariations in the output current of unit transistors 484 based onmeasurement results. The variations in the output current are variationsin current at a threshold voltage (Vt). Black dots indicate variationsin the output current of evaluation sample transistors (10 to 200 innumber) created in a formation area. There is almost no variation(output current variations only within a margin of error, meaning that aconstant output current is produced) in the output current oftransistors formed in area A (a formation area of 0.5 square millimetersor less) in FIG. 110. Conversely, in area C (a formation area of 2.4square millimeters or more), variations in the output current withrespect to the formation area tend to increase sharply. In area B (aformation area of 0.5 to 2.4 square millimeters), variations in theoutput current are almost proportional to the formation area.

However, the absolute value of output current varies from wafer towafer. However, this problem can be dealt with by adjusting thereference voltage or setting it to a fixed value in the source drivercircuit (IC) 14 of the present invention. Also, it can be dealt with(solved) by modifying the current mirror circuit ingeniously.

The present invention varies (controls) the amount of current flowingthrough the source signal line 18 by switching the number of currentsflowing through the unit transistors 634 using input digital data (D).When the number of gradations is 64 or more, since 1/64=0.015,theoretically variations in output current should be within 1 to 2%.Incidentally, output variations within 1% are difficult to distinguishvisually and output variations of 0.5% or below are impossible todistinguish (look uniform).

To keep output current variations (%) within 1%, the formation area of atransistor group (the transistors among which variations should besuppressed) should be kept within 2 square millimeters as indicated bythe results shown in FIG. 110. More preferably, the output currentvariations (i.e., variations in the Vt of transistors) should be keptwithin 0.5%. That is, the formation area of a transistor group 681 canbe kept within 1.2 square millimeters as indicated by the results shownin FIG. 110. Incidentally, the formation area is given by the verticallength multiplied by the horizontal length. For example, a formationarea of 1.2 square millimeters results from 1 mm×1.2 mm.

Incidentally, the above applies to 8-bit (256 gradations) or largerdata. For a smaller number of gradations, for example, in the case of6-bit data (64 gradations), variations in output current may besomewhere around 2% (virtually no problem in terms of image display). Inthis case, the formation area of a transistor group 681 can be keptwithin 5 square millimeters. There is no need for the two transistorgroups 681 (transistor groups 681 a and 681 b are shown in FIG. 68) tosatisfy this condition. Effect of the present invention can be achievedif at least one of the transistor groups (one or more transistor groups681 if there are more than three) satisfy the condition. Preferably,this condition should be satisfied for a lower level transistor group681 (681 a is higher than 681 b). This will reduce image displayproblems.

In the source driver circuit (IC) 14 of the present invention, at leasta plurality of current sources, such as consisting of parent, child, andgrandchild current sources, are connected in multiple stages (of coursethere may be two stages consisting of parent and child current sources)and placed densely, as shown in FIG. 68. Current-based delivery is madebetween current sources (between the transistor groups 681).Specifically, transistors enclosed by dotted lines in FIG. 68(transistor groups 681) are placed densely. The transistor groups 681make voltage-based delivery between each other. The parent currentsource 631 and child current sources 632 a are formed (placed)approximately in the center of the source driver IC chip 14. This makesit possible to relatively shorten the distance between the transistors632 a composing the child current sources placed on the left and rightof the chip and the transistors 632 b composing current child sources.That is, the top-level transistor group 681 a is placed at theapproximate center of the IC chip. Then, lower-level transistor groups681 b are placed on the left and right of the IC chip 14. Preferably,the transistors are placed, formed, or produced in such a way thatapproximately equal numbers of lower-level transistor groups 681 b willbe on the left and right of the IC chip 14. Incidentally, the aboveitems are not limited to IC chips 14, but apply to source drivercircuits 14 formed directly on array boards 71 using low-temperaturepolysilicon technology or high-temperature polysilicon technology. Thesame is true of the other items.

According to the present invention, one transistor group 681 a isconstructed, placed, formed, or built at the approximate center of theIC chip 14 and eight transistor groups 681 b each are formed on the leftand right of the chip (N=8+8, see FIG. 63). Preferably the childtransistor groups 681 b are arranged in such a way that their numberswill be equal on the left and right of the chip or that the differencebetween the number of the child transistor groups 681 b formed or placedon the left with respect to the center of the chip where the parent isformed and the number of the child transistor groups 681 b formed orplaced on the right of the chip will be four or less. More preferably,the difference between the number of the child transistor groups 681 bformed or placed on the left of the chip and the number of the childtransistor groups 681 b formed or placed on the right of the chip is oneor less. The above items similarly apply to grandchild transistor groups(omitted in FIG. 68).

Voltage-based delivery (voltage connection) is made between the parentcurrent source 631 and child current sources 632 a. Consequently, tendsto be affected by variations in the Vt of the transistors. Thus, thetransistors in the transistor group 681 a are placed densely. Theformation area of the transistor group 681 a is kept within 2 squaremillimeters as shown in FIG. 110. More preferably, it is kept within 1.2square millimeters. If the number of gradations is 64 or less, ofcourse, the formation area may be within 5 square millimeters.

Data is delivered between the transistor group 681 a and childtransistors 632 b via current, and thus the current may flow somedistance. Regarding the distance (e.g., between the output terminals ofthe higher-level transistor group 681 a and input terminals of thelower-level transistor group 681 b), the transistors 632 a composing thesecond current sources (child) and the transistors 632 b composing thesecond current sources (child) should be placed at least within 10 mm ofeach other as described above. Preferably, the transistors should beplaced or formed within 8 mm. More preferably, they should be placedwithin 5 mm.

It has been shown analytically that differences in characteristics (Vtand mobility (μ)) of transistors placed in a silicon chip do not havemuch impact in the case of current-based delivery if the distance iswithin this range. Preferably, the above conditions are satisfiedespecially by lower-level transistor groups. For example, if thetransistor group 681 a is at the top level with the transistor groups681 b lying below it and transistor groups 681 c lying further belowthem, the current-based delivery between the transistor groups 681 b andtransistor groups 681 c should satisfy the above conditions. Thus,according to the present invention it is not always necessary that allthe transistor groups 681 satisfy the above conditions. It is sufficientthat at least a pair of transistor groups 681 satisfy the aboveconditions. This is because the lower the level, the more transistorgroups 681 there are.

This similarly applies to the transistors 633 a constituting the third(grandchild) current sources and transistors 633 b constituting thethird current sources. Needless to say, almost the same applies tovoltage-based delivery. The transistor groups 681 b are formed, built,or placed in the left-to-right direction of the chip (in thelongitudinal direction, i.e., at locations facing the output terminal761). The transistor groups 681 b are formed, built, or placed in theleft-to-right direction of the chip (in the longitudinal direction,i.e., at locations facing the output terminal 761). According to thepresent invention, the number M of the transistor groups 681 b is 11(see FIG. 63).

Voltage-based delivery (voltage connection) is made between the childcurrent sources 632 b and grandchild current sources 633 a. Thus, thetransistors in the transistor groups 681 b are placed densely as is thecase with the transistor group 681 a. The formation area of thetransistor group 681 b should be within 2 square millimeters as shown inFIG. 110. More preferably, it should be within 1.2 square millimeters.However, even slight variations in the Vt of the transistors in thetransistor groups 681 b tend to appear on the screen. Thus, preferablythe formation area should be area A (0.5 square millimeters or less) inFIG. 110.

Data is delivered between the grandchild transistors 633 a andtransistors 633 b (current-based delivery), and thus the current mayflow some distance in the transistor group 681 b. The description ofdistances provided earlier applies here as well. The transistors 633 aconstituting the third (grandchild) current sources and transistors 633b constituting the second (grandchild) current sources should be placedwithin at least 8 mm of each other. More preferably, they should beplaced within 5 mm.

FIG. 69 shows the current-value adjustment element constituted of anelectronic regulator. The electronic regulator consists of a resister691 (which is formed of polysilicon, controls current, and createsreference voltages), decoder circuit 692, level-shifter circuit 693,etc. Incidentally, the electronic regulator outputs current. Atransistor 641 functions as an analog switch circuit.

Incidentally, in the source driver IC (circuit) 14, transistors may bereferred to as current sources. This is because transistors function ascurrent sources in current mirror circuits and the like composed oftransistors.

Electronic regulators circuits are formed (or placed) according to thenumber of colors used by the EL display panel. For example, if the threeprimary colors RGB are used, preferably three electronic regulators areformed (or placed) corresponding to the colors so that the colors can beadjusted independently. However, if one color is used as a reference (isfixed), as many electronic regulators circuits as the number of colorsminus 1 should be formed (or placed).

FIG. 76 shows a configuration in which resistive elements 651 are formed(or placed) to control reference voltages of the three primary colorsRGB independently. Of course, it goes without saying that the resistiveelements 651 may be substituted with electronic regulators. Basiccurrent sources including parent and child current sources such as thecurrent source 631 and current sources 632 are placed densely in anoutput current circuit 704 in an area illustrated in FIG. 76. The denseplacement reduces variations in outputs from the source signal lines 18.As illustrated in FIG. 76, by placing them in the output current circuit704 at the center of the source driver IC (circuit) 14, it becomes easyto distribute current to the left and right of the source driver IC(circuit) 14 from the current source 631 and current sources 632,resulting in reduced output variations between the left and right sides(it is all right to place them in a reference current generator circuitor controller instead of the current output circuit. That is, 704 is anarea where an output circuit is not formed).

However, it is not always necessary to place them in the output currentcircuit 704 at the center They may be placed at an end or both ends ofthe IC chip. Also, they may be formed or placed in parallel with theoutput current circuit 704.

It is not desirable to form a controller or output current circuit 704in the center of the IC chip 14 because they are liable to be affectedby Vt distribution of the unit transistors 634 in the IC chip 14 (the Vtof an wafer is distributed evenly in the wafer).

Reasons for this will be described with reference to FIG. 120. If thecontroller or output current circuit 704 is formed in the center of theIC chip 14, it is not possible to form or construct an output currentcircuit constituted of unit transistors 634 in the center. On the otherhand, pixels 16 are formed in a matrix in the display screen 50 of thedisplay panel. The pixels are formed in a grid pattern at equalintervals. Consequently, as illustrated in FIG. 120, there is no outputterminal 761 b of the output current circuit in the center of the ICchip 14. Thus, wires are routed to the center portion of the displayscreen 50 of the display panel from output terminals 761 a and 761 cother than those in the center of the EL element 15.

However, there is a possibility that the unit transistors of the outputcircuits connected to the output terminals 761 b and 761 c differ in Vt.Even if the unit transistors 634 of the output terminals have equal gateterminal voltage, their output current will vary depending on the Vtdistribution of the unit transistors 634. Consequently, there may besteps of output currents in the center of the panel. The steps of outputcurrents can cause brightness difference between the right and leftsides in the center of the screen.

A configuration used to solve this problem is shown in FIG. 122. FIG.122(a) shows an exemplary configuration in which an output currentcircuit 704 is placed on one side of an IC chip. FIG. 122(b) shows anexemplary configuration in which output current circuits 704 are placedon both sides of an IC chip. FIG. 122(c) shows an exemplaryconfiguration in which an output current circuit 704 is placed on theside of input terminals of an IC chip. Thus, output terminals are formedorderly in areas not occupied by the output current circuits 704.

In the circuit configuration in FIG. 68, transistors 633 a andtransistors 633 b are connected in a one-to-one completion. In FIG. 67again, transistors 632 a and transistors 632 b are connected in aone-to-one completion.

However, if transistors are connected in a one-to-one relationship withother transistors, any variation in the characteristics (Vt, etc.) ofcharacteristics of a transistor will result in variations in the outputof the corresponding transistor connected to it.

To solve this problem, an example with an appropriate configuration isshown in FIG. 123. In the configuration shown in FIG. 123, transmissiontransistor groups 681 b (681 b 1, 681 b 2, and 681 b 3) each of whichconsists of four transistors 633 a and transmission transistor groups681 c (681 c 1, 681 c 2, and 681 c 3) each of which consists of fourtransistors 633 b are connected with each other. Although it has beenstated that each of the transistor groups 681 b and 681 c consist offour transistors 633, this is not restrictive and may consist of lessthan four or more than four transistors. That is, a reference current Ibflowing through the transistors 633 a is output from a plurality oftransistors 633 which form a current mirror circuit together with thetransistors 633 a and the output current is received by a plurality oftransistors 633 b.

Preferably, the plurality of transistors 633 a and plurality oftransistors 633 b are approximately equal in size and equal in number.Preferably, the unit transistors 634 (63 in number in the case of 64gradations as in FIG. 124) each of which produces one output and thetransistors 633 b which compose a current mirror together with the unittransistors 634 are also approximately equal in size and equal innumber. The above configuration makes it possible to set a currentmirror ratio accurately and reduce variations in output current.

Preferably, the current flowing through the transistors 633 b is equalto or more than five times a current Ic1 passed through the transistors632 b. This will stabilize the gate potential of the transistors 633 aand suppress transient phenomena caused by output current.

Although it has been stated that the transmission transistor group 681 b1 and transmission transistor group 681 b 2 are placed adjacent to eachother and that each of them consists of four transistors 633 a placednext to one another, this is not restrictive. For example, thetransistors 633 a of the transmission transistor group 681 b 1 and thetransistors 633 a of the transmission transistor group 681 b 2 may beplaced or formed alternately. This will reduce variations in the outputcurrent (programming current) of each terminal.

The use of multiple transistors for current-based delivery makes itpossible to reduce variations in output current of the transistor groupas a whole and further reduce variations in the output current(programming current) of each terminal.

The total formation area of the transistors 633 composing a transmissiontransistor group 681 is an important item. Basically, the larger thetotal formation area of the transistors 633, the smaller the variationsin output current (programming current flowing in from the source signalline 18). That is, the larger the formation area of the transmissiontransistor group 681 (the total formation area of the transistors 633),the smaller the variations. However, a larger formation area of thetransistors 633 increases a chip area, increasing the price of the ICchip 14.

Incidentally, the formation area of a transmission transistor group 681is the sum total of the formation areas of the transistors 633 composingthe transmission transistor group 681. The area of a transistor 633 isthe product of the channel length L and channel width W of thetransistor 633. Thus, if a transistor group 681 consists of tentransistors 633 whose channel length L is 10 μm and channel width W is 5μm, the formation area Tm (square μm) of the transmission transistorgroup 681 is 10 μm×5 μm×10=500 (square μm).

The formation area of the transmission transistor group 681 should bedetermined in such a way as to maintain a certain relationship with theunit transistors 634. Also, the transmission transistor group 681 a andtransmission transistor group 681 b should maintain a certainrelationship.

Now, description will be given of the relationship between the formationarea of the transistor group 681 and the unit transistors 634. As alsoillustrated in FIG. 66, a plurality of unit transistors 634 areconnected per one transistor 633 b. In the case of 64 gradations, 63unit transistors 634 correspond to one transistor 633 b (configurationin FIG. 64). If the channel length L of the unit transistor 633 is 10 μmand channel width W of the unit transistor 633 is 10 μm, the formationarea Ts (square μm) of the unit transistor group is 10 μm×10 μm×63=6300square μm.

The transistor 633 b in FIG. 64 and transmission transistor groups 681 cin FIG. 123 are relevant here. The formation area Ts of the unittransistor group and formation area Tm of the transmission transistorgroup 681 c have the following relationship:1/4≦Tm/Ts≦6

More preferably, the formation area Ts of the unit transistor group andformation area Tm of the transmission transistor group 681 c have thefollowing relationship:1/2≦Tm/Ts≦4

By satisfying the above relationship, it is possible to reducevariations in the output current (programming current) of each terminal.

Also, the formation area Tmm of the transmission transistor group 681 band formation area Tms of the transmission transistor group 681 c havethe following relationship:1/2≦Tmm/Tms≦8

More preferably, the formation area Ts of the unit transistor group andformation area Tm of the transmission transistor group 681 c have thefollowing relationship:1≦Tm/Ts≦4

By satisfying the above relationship, it is possible to reducevariations in the output current (programming current) of each terminal.

Suppose output current from the transistor group 681 b 1 is Ic1, outputcurrent from the transistor group 681 b 2 is Ic2, and output currentfrom the transistor group 681 b 2 is Ic3. Then, the output currents Ic1,Ic2, and Ic3 must coincide. According to the present invention, sinceeach transistor group 681 consists of multiple transistors 633, even ifindividual transistors 633 have variations, there is no variation in theoutput current Ic of the transistor group 681 as a whole.

Incidentally, the above example is not limited to three-stage currentmirror connections (multi-stage current mirror connections) shown inFIG. 68. Needless to say, it is also applicable to single-stage currentmirror connections. The example shown in FIG. 123 involves connectingthe transistor groups 681 b (681 b 1, 681 b 2, 681 b 3, . . . ) each ofwhich consists of multiple transistors 633 a with the transistor groups681 c (681 c 1, 681 c 2, 681 c 3, . . . ) each of which consists ofmultiple transistors 633 b. However, the present invention is notlimited to this. It is also possible to connect a single transistor 633a with the transistor groups 681 c (681 c 1, 681 c 2, 681 c 3, . . . )each of which consists of multiple transistors 633 b, or to connect thetransistor groups 681 b (681 b 1, 681 b 2, 681 b 3, . . . ) each ofwhich consists of multiple transistors 633 a with one transistor group633 b.

In FIG. 64, the switch 641 a corresponds to the 0th bit, the switch 641b corresponds to the 1st bit, the switch 641 c corresponds to the 2ndbit, . . . , and the switch 641 f corresponds to the 5th bit. The 0thbit consists of one unit transistor, the 1st bit consists of two unittransistor, the 2nd bit consists of four unit transistor, . . . , andthe 5th bit consists of thirty-two (32) unit transistor. For ease ofexplanation, it is assumed that the source driver circuit 14 is a 6-bitdriver supporting 64-gradation display.

With the configuration of the driver 14 according to the presentinvention, the 1st bit outputs a twice larger programming current to the0th bit, the 2nd bit outputs a twice larger programming current to the1st bit, the 3rd bit outputs a twice larger programming current to the2nd bit, the 4th bit outputs a twice larger programming current to the3rd bit, the 5th bit outputs a twice larger programming current to the4th bit. To put it in other words, each bit must be able to output twiceas large programming current as the next lower-order bit.

However, in practice because of variations in the unit transistors 634constituting different bits, it is difficult (if not impossible) toconfigure such that each terminal will output exactly twice largerprogramming current. An example which can solve this problem is shown inFIG. 124.

The configuration in FIG. 124 contains adjustment transistors inaddition to the unit transistors 634 for individual bits. The adjustmenttransistors 1241 correspond to the 5th bit (switch 641 f) and 4th bit(switch 641 e).

In the example shown in FIG. 124, the adjustment transistors 1241 areplaced, formed, or constructed at the 5th bit (the unit transistors 634connected to the switch 641 f) and 4th bit (the unit transistors 634connected to the switch 641 d). Four adjustment transistors 1241 eachare placed or formed at the 5th bit and 4th bit. However, the presentinvention is not limited to this. The number of adjustment transistors1241 for each bit maybe changed. Also, adjustment transistors 1241 maybe attached to all the bits (by forming, constructing, or placing them).The adjustment transistors 1241 are made smaller than the unittransistors 634. Alternatively, they are designed to produce smalleroutput current than the unit transistors 634. Even if transistor size isfixed, it is possible to vary output current by varying W/L.

Incidentally, the adjustment transistors 1241 and unit transistors 634are configured or connected so as to share gate terminals, to which thesame gate voltage is applied. Thus, when a current Ib flows through thetransistors 633, the gate voltage of the unit transistors 634 isestablished, prescribing the current to be output from the unittransistors 634. At the same time, output current of the adjustmenttransistors 1241 is also defined. That is, the output current of theadjustment transistors 1241 is proportional to the output current of theunit transistors 634. The output current can be controlled by means ofthe current Ib to be passed to the transistors 633 which pair up withthe unit transistors 634.

According to the present invention, the size of one unit transistor 634is made larger than the total size of two or more adjustmenttransistors. That is, the size of the unit transistor 634 is larger thanthe size of the adjustment transistor 1241. Alternatively, the totalsize of two or more adjustment transistors 1241 is made larger than thesize of the unit transistor 634. By controlling the number of workingadjustment transistors 1241, it is possible to adjust variations inoutput current for each bit in small increments.

According to another example of the present invention, the outputcurrent of one unit transistor 634 is made larger than the outputcurrent of two or more adjustment transistors. That is, the outputcurrent of the unit transistor 634 is larger than the output current ofthe adjustment transistor 1241. By controlling the number of workingadjustment transistors 1241, it is possible to adjust variations inoutput current for each bit in small increments.

FIG. 125 is an explanatory diagram illustrating a method of adjustingthe output current for each bit using the adjustment transistors 1241.

FIG. 125 shows four adjustment transistors 1241 which have been formed.Incidentally, it is assumed for ease of explanation that a target outputcurrent of the bit for output current adjustment is Ia and that actualoutput current Ib is smaller than the target output current Ia by Ie(Ia=Ib+Ie). Also, if Ig is current which flows when all the fouradjustment transistors 1241 operate normally, Ig>Ie should always besatisfied even if there are variations in production processes oftransistors. Thus, when the four adjustment transistors 1241 are inoperation, the output current Ib exceeds the target output current Ia(Ib>Ia).

In the above condition, adjustment transistors 1241 are cut off from thecommon terminal 1252 to obtain the target output current Ia. Lasercutting is used to cut off the adjustment transistors 1241. It isappropriate to use a YAG laser for the laser cutting. Besides, neonhelium lasers and carbon dioxide lasers are also available. Also,machining such as sand blasting is available as well.

In FIG. 125, the transistors 1241 a and 1241 b are cut off from thecommon terminal 1252 at two cutting sites 1251. Consequently, thecurrent Ig is halved. In this way, adjustment transistors 1241 are cutoff one by one from the common terminal 1252 until the target outputcurrent Ia is obtained. The output current is measured with amicroammeter to stop cutting off adjustment transistors 1241 when themeasured value reaches the target value.

Incidentally, although it has been stated with reference to FIG. 125that the cutting sites 1251 are cut with laser to adjust the outputcurrent, this is not restrictive. For example, laser may be emitteddirectly to adjustment transistors 1241 to adjust the output current bydestroying them. It is also possible to provide analog switches at thecutting sites 1251, turn on and off the analog switches by externalcontrol signals, and thereby vary the number of adjustment transistors1241 to be connected to point g. That is, the present invention formsadjustment transistors 1241 and obtains target output current by turningon and off the adjustment transistors 1241. Thus, needless to say, otherconfigurations can also be used.

Also, it is not strictly necessary to perform cutting at the cuttingsites 1251, and it is alternatively possible to open the cutting sitesin advance and make connections by depositing a metal film or the likeon the cutting sites.

Besides, although it has been stated that the adjustment transistors1241 are formed in advance, this is not restrictive. For example, it isalso possible to trim part of the unit transistors 634, and therebyadjust the output current of the unit transistors 634 so as to obtainthe target output current for each bit. Alternatively, it is possible toobtain the target output currents for different bits by separatelyadjusting the gate terminal voltages of the unit transistors 634 whichcorrespond to the respective bits. For example, this can be accomplishedby trimming the wiring connected to the gate terminals of the unittransistors 634 and thereby increasing resistance.

FIG. 166 illustrates part of the adjustment transistors 1241 or unittransistors 634. A plurality of unit transistors 634 (or the adjustmenttransistors 1241) are connected via internal wiring 1622. The adjustmenttransistors 1241 have a slit cut in their source terminals (S terminals)for ease of trimming. By making a cut at a cutoff point 1661 b, it ispossible to limit the current flowing between channels of the adjustmenttransistors 1241. This decreases output current in a current outputstage 704. Incidentally, a slit may be formed not only in the sourceterminal, but also in the drain or gate terminal. Needless to say, partof the adjustment transistors 1241 can be cut off even if no slit isformed. It is also possible to form a plurality of adjustmenttransistors 1241 of different shapes, trim the adjustment transistors1241 after measurement of output current, and thereby select thetransistors which will produce output current closest to the targetoutput current.

Incidentally, although unit transistors 634 or adjustment transistors1241 are trimmed to adjust output current in the above example, thepresent invention is not limited to this. For example, it is possible toform adjustment transistors 1241 in isolation, connect their sourceterminals or the like to output current circuits 704 by a FIB process,and thereby adjust output current. However, there is no need to isolatethe adjustment transistors 1241 completely. For example, it is possibleto form output current circuits 704 and adjustment transistors 1241 withtheir gate terminals and source terminals connected and connect thedrain terminals of the adjustment transistors 1241 by a FIB process.

Also, it is possible to construct the gate terminals of adjustmenttransistors 1241 in isolation from the gate terminals of unittransistors 634, which form the output current circuits 704, and form orplace the unit transistors 634 and the adjustment transistors 1241 withtheir drain terminals and source terminals connected. The potential atthe gate terminals of the unit transistors 634 is determined by currentIc as illustrated in FIG. 164 and the like. The potential at the gateterminals of the adjustment transistors 1241 can be adjusted freely. Byadjusting this potential, it is possible to change the output current ofthe adjustment transistors 1241. Thus, by adjusting the potential at thegate terminals of the adjustment transistors 1241, it is possible toadjust the output current of the output current circuits 704, which is asum total of the output currents from the unit transistors 634 andadjustment transistors 1241. This method does not require a trimmingprocess or FIB process. The gate terminal voltage of the adjustmenttransistors 1241 may be adjusted using an electronic regulator or thelike.

Although it has been stated that the output current of the adjustmenttransistors 1241 is adjusted through adjustment of the potential at thegate terminals, this is not restrictive. The output current may beadjusted through adjustment of the voltage applied to the sourceterminals or drain terminals of the adjustment transistors 1241. Theseterminal voltages may also be adjusted using an electronic regulator.Also the voltages applied to the terminals of the adjustment transistors1241 are not limited to direct-current voltages. It is also possible toapply rectangular voltages (pulsed voltages or the like) and controloutput voltages by duration control.

To change the magnitude of output current greatly, the adjustmenttransistors 1241 may be cut off at a cutoff point 1661 a as illustratedin FIG. 166. In this way, by trimming all or part of the unittransistors 634 or adjustment transistors 1241, it is possible to adjustthe output current easily. To protect trimming sites from degradation,it is recommended to seal them by vapor-depositing or applying inorganicor organic material to them after trimming so that they will not beexposed to the air.

In particular, preferably the output current circuits 704 on both endsof the IC chip 14 are equipped with a trimming function. In the case ofa large display panel, a plurality of source driver ICs 14 must becascaded. This is because cascade connection makes any differencebetween output currents of adjacent ICs conspicuous as a boundary. Bytrimming transistors and the like as illustrated in FIG. 166, it ispossible to correct output current variations among adjacent outputcurrent circuits.

Needless to say, the above is also applicable to other examples of thepresent invention.

The configuration in FIG. 123 reduces variations in the output currentof each terminal by making a plurality of transistors 633 b receiveoutput current from a plurality of transistors 633 a. FIG. 126 shows aconfiguration which reduces variations in the output current of eachterminal by supplying current from both sides of a transistor group.Multiple sources are provided for current Ia. Current Ia1 and currentIa2 have the same current value and the transistor which generates thecurrent Ia1 and the transistor which generates the current Ia2 compose acurrent mirror circuit as a pair.

Thus, in this configuration, a plurality of transistors (currentgenerating means) are formed, placed, or constructed to generatereference currents which prescribe output currents of the unittransistors 634. More preferably, output currents from the plurality oftransistors are connected to current-receiving circuits such astransistors which compose current mirror circuits and the outputcurrents of the unit transistors 634 are controlled by gate voltagesgenerated by the plurality of transistors.

Further, an embodiment according to FIG. 126 shows transistors 633 bcomposing current mirror circuits are formed on both sides of the groupof the unit transistors 634. However, the present invention is notlimited to this. A configuration in which transistors 632 a composingcurrent mirrors are placed on both sides of a transistor group 681 balso belongs to the present invention.

As can be seen from FIG. 126, the transistor group 681 b contains aplurality of transistors 633 a which output current. On both sides ofthe transistor group 681 b, there are transistors 632 a (632 a 1 and 632a 2) which share the gate terminals of the transistor group 681 b andform current mirrors circuit in conjunction with transistors 633 a.

A reference current Ia1 flows through the transistor 632 a 1 and areference current Ia2 flows through the transistor 632 a 2. Thus, thegate terminal voltage of the transistors 633 a (633 a 1, 633 a 2, 633 a3, 633 a 4, . . . ) a redefined by the transistors 632 a 1 and 632 a 2,and define the current outputted from the transistors 633 a.

The magnitudes of the reference currents Ia1 and Ia2 are made tocoincide. This can be accomplished by constant-current circuits such asthe current mirror circuit which output the reference currents Ia1 andIa2.

Even if the reference currents Ia1 and Ia2 deviate more or less fromeach other, this poses little problem because they correct each other.

Although it has been stated in the above example that the referencecurrents Ia1 and Ia2 are made to roughly coincide, the present inventionis not limited to this. For example, the reference currents Ia1 and Ia2may be different from each other. For example, if the current Ia1 issmaller than the current Ia2, a current Ib1 outputted by a transistor633 a 1 can be made smaller than a current Ibn outputted by a transistor633 an (Ib1<Ibn). The smaller the current Ib1, the smaller the currentoutputted by a transistor group 681 c 1. The larger the current Ibn, thelarger the current outputted by a transistor group 681 cn. Thetransistor groups 681 placed or formed between the transistor group 681c 1 and transistor group 681 cn produce output currents of intermediatemagnitudes.

Thus, by making the current Ia1 and current Ia2 different from eachother, it is possible to produce a slope in the output currents of thetransistor groups 681. The sloping of the output currents of thetransistor groups 681 is effective for cascade connection of the sourcedriver ICs 14. This is because adjustments of the two reference currentsIa1 and Ia2 for IC chips make it possible to adjust the output currentsof the output current circuits 704. Thus, it is possible to makeadjustments so as to eliminate differences between output currents ofadjacent ICs chip 14.

Even if the current Ia1 and current Ia2 are made different from eachother, if the potentials at the gate terminals of the unit transistors634 in the transistor groups 681 are equal, it is not possible toproduce a slope in the output currents of the transistor groups 681. Thereason why a slope is produced in the output currents of the transistorgroups 681 is that the gate terminal voltage differs among the unittransistors 634. To vary the gate terminal voltage, it is necessary toincrease the resistance of gate wiring 1261 in the transistor group 681b. Specifically, the gate wiring 1261 is formed of polysilicon. Also,the resistance value of the gate wiring between the transistors 632 a 1and 632 an should be between 2 KΩ and 2 MΩ (both inclusive). In thisway, by increasing the resistance of the gate wiring 1261, it ispossible to produce a slope in the output currents of the transistorgroups 681 c.

Preferably, the gate terminal voltage of the transistor 633 a is set at0.52 to 0.68 V (both inclusive) is a silicon IC chip is used. This rangecan reduce variations in the output current of the transistor 633 a. Theabove items similarly apply to other examples of the present invention.

Needless to say, the above items also apply to other examples of thepresent invention.

In the configuration shown in FIG. 126, the current mirror circuitcontains two or more (multiple) transistors 632 a which pair with thetransistors 633 a. Since reference current are supplied from both sides,the gate terminal voltage of the transistors 633 a is kept constantreliably in the transistor group 681 a. Consequently, variations in theoutput current produced by the transistors 633 a are extremely small.Thus, there are extremely small variations in the programming currentoutputted to the source signal line 18 or programming current drawn fromthe source signal line 18.

In FIG. 126, current is transferred between the transistor 633 a 1 andtransistor 633 b 1 as well as between the transistor 633 a 2 andtransistor 633 b 2. Thus, the transistor group 681 c 1 is alsoconfigured to be supplied with current from both sides. Similarly,current is transferred between the transistor 633 a 3 and transistor 633b 3 as well as between the transistor 633 a 4 and transistor 633 b 4.Also, current is transferred between the transistor 633 a 5 andtransistor 633 b 5 as well as between the transistor 633 a 6 andtransistor 633 b 6.

The transistor groups 681 c constitute output-stage circuits connectedto respective source signal lines 18. Thus, by supplying current to thetransistor groups 681 c from both sides and eliminating voltage drops orpotential distribution of the gate terminals of the unit transistors634, it is possible to do away with variations in output currents fromthe source signal lines 18.

Each transistor group 681 c contains a plurality of unit transistors 634which output current. On both sides of the transistor group 681 c, thereare transistors 633 b (633 b 1 and 633 b 2) which share the gateterminals of the transistors 634 and form current mirror circuits inconjunction with the transistors 634. The reference current Ib1 flowsthrough the transistor 633 b 1 and the reference current Ib2 flowsthrough the transistor 633 b 2. Thus, the gate terminal voltage of theunit transistors 634 are defined by the transistors 633 b 1 and 633 b 2,and define the current outputted from the unit transistors 634.

The magnitudes of the reference currents Ib1 and Ib2 are made tocoincide. This can be accomplished by constant-current circuits such asthe transistors 633 a which output the reference currents Ib1 and Ib2.Even if the reference currents Ib1 and Ib2 deviate more or less fromeach other, this poses little problem because they correct each other.

FIG. 127 shows a variation of the example shown in FIG. 126. In FIG.127, there is a transistor 632 which forms a current mirror circuit inthe middle of the transistor group 681 b in addition to the transistors632 a which form current mirror circuits on both sides of the transistorgroup 681 b. Consequently, the transistors 633 a have a more constantgate terminal voltage and less variations in its output, compared withthe configuration shown in FIG. 126.

Needless to say, the above items are also applicable to the transistorgroups 681 c.

FIG. 128 shows another variation of the example shown in FIG. 126. InFIG. 126, the transistors 633 a in the transistor group 681 b areconnected in sequence with the transistors 633 b which form currentmirror circuits in conjunction with the transistor groups 681 c.

In the example shown in FIG. 128, the transistors 633 a are connected ina different order.

In FIG. 128, the transistor 633 a 1 performs current-based deliveryto/from the transistor 633 b 1 which form a current mirror circuit inconjunction with the transistor group 681 c 1. The transistor 633 a 2performs current-based delivery to/from the transistor 633 b 3 whichform a current mirror circuit in conjunction with the transistor group681 c 2. The transistor 633 a 3 performs current-based delivery to/fromthe transistor 633 b 2 which form a current mirror circuit inconjunction with the transistor group 681 c 1. The transistor 633 a 4performs current-based delivery to/from the transistor 633 b 5 whichform a current mirror circuit in conjunction with the transistor group681 c 3. The transistor 633 a 5 performs current-based delivery to/fromthe transistor 633 b 4 which form a current mirror circuit inconjunction with the transistor group 681 c 2.

With the configuration shown in FIG. 126, any characteristicdistribution of the transistors 633 a tends to cause the transistorgroups 681 c supplied with current from the transistors 633 a to formblocks, resulting in changes in output current. Consequently,block-shaped boundaries may appear on the EL display panel.

As shown in FIG. 128, by rearranging the order of connection with thetransistors 633 which form current mirror circuits in conjunction withthe transistor groups 681 c instead of connecting the transistors 633 ain order, it is possible to reduce changes in output current caused byblocks formed by the transistor groups 681 c even if there ischaracteristic distribution of the transistors 633 a. This preventsblock-shaped boundaries from appearing on the EL display panel.

Of course, the transistors 633 a and transistors 633 b need not beconnected regularly, and may be connected randomly. Besides, thetransistors 633 a may be connected with the transistors 633 b byskipping two or more instead of skipping one as shown in FIG. 128.

In the above example, current mirror circuits are connected in multiplestages as illustrated in FIG. 68. However, the present invention is notlimited to multi-stage circuit configurations and can employsingle-stage circuit configurations as illustrated in FIG. 129.

FIG. 129 controls or adjusts a reference current by a reference currentregulating means 651 (which, needless to say, is not limited to avariable regulator, and may be an electronic regulator). The unittransistors 634 form current mirror circuits in conjunction with thetransistors 633 b. The reference current Ib defines the magnitude ofoutput current from the unit transistors 634.

With the configuration shown in FIG. 129, the reference current Ibcontrols the currents of the unit transistors 634 in the transistorgroups 681 c. To put it in other words, the transistors 633 b define theprogramming current for the unit transistors 634 in the transistorgroups 681 c 1 to 681 cn.

However, there are often subtle differences between the gate terminalvoltage of the unit transistors 634 in the transistor group 681 c 1 andthe gate terminal voltage of the unit transistors 634 in the transistorgroup. This is presumed to be due to voltage drops and the like causedby current flowing through the gate wiring and the like. Even a subtlechange in voltage will result in a few percent change in output current(programming current). According to the present invention, differenceamong gradations is 1.5% (=100/64) in the case of 64 gradations. Thus,changes in output current should be reduced to at least on the order of1% or less.

A configuration used to solve this problem is shown in FIG. 130. In FIG.130, there are two generator circuits of the reference current Ib. Areference current generator circuit 1 delivers reference current Ib1 anda reference current generator circuit 2 delivers reference current Ib2.The reference current Ib1 and reference current Ib2 have the samecurrent value. The reference currents are controlled or adjusted by areference current regulating means 651 (which, needless to say, is notlimited to a variable regulator, and maybe an electronic regulator.Alternatively, the reference currents may be adjusted by changing fixedresistors). Incidentally, the output terminals of the transistor groups681 c are connected to the source signal lines 18. The configurationused here is a single-stage current mirror circuit.

However, if the reference current Ib1 and reference current Ib2 areconfigured to be separately adjustable, it is possible to adjust outputcurrent (programming current) to be uniform when voltage at point a andvoltage at point b on a common terminal 1253 differ from each other andthe unit transistors 634 in the transistor group 681 c 1 and unittransistors 634 in the transistor group 681 c 2 differ in outputcurrent. Also, since unit transistors on left and right sides of the ICchip 14 differ in Vt, it is possible to eliminate a slope in outputcurrent and correct any slope which is produced.

Although two reference current generator circuits are formed separatelyin FIG. 130, this is not restrictive and they may be constructed of thetransistors 633 a in the transistor group 681 b shown in FIG. 128. Byusing the configuration in FIG. 128 and controlling (adjusting) thecurrent passed through the transistors 632 a composing current mirrors,it is possible to simultaneously control (adjust) the reference currentsIb1 and Ib2 shown in FIG. 130. That is, the transistors 633 b 1 and 633b 2 are controlled as a transistor group (see FIG. 130(b)).

The use of the configuration in FIG. 130 makes it possible to equalizethe voltage at point a and voltage at point b on the common terminal1253 (gate wiring 1261). This makes it possible to equalize the outputcurrent of the unit transistors 634 in the transistor group 681 c 1 andthe output current of the unit transistors 634 in the transistor group681 c 2 and supply uniform programming current free of variations to thesource signal lines 18.

In this way, the configuration in FIG. 130 contains two referencecurrent sources. FIG. 131 shows a configuration in which gate voltage ofa transistor 633 b constituting a reference current source is applied tothe center of the common terminal 1253 as well.

The reference current generator circuit 1 delivers the reference currentIb1 and the reference current generator circuit 2 delivers the referencecurrent Ib2.

A reference current generator circuit 3 delivers reference current Ib3.The reference current Ib1, reference current Ib2, and reference currentIb3 have the same current value. The reference currents are controlledor adjusted by a reference current regulating means 651 (which, needlessto say, is not limited to a variable regulator, and may be an electronicregulator).

If the reference current Ib1, reference current Ib2, and referencecurrent Ib3 are configured to be separately adjustable, it is possibleto adjust the gate terminal voltage of the transistor 633 b 1,transistor 633 b 2, and transistor 633 b 3. It is possible to adjust thevoltage at point a, voltage at point b, and voltage at point c on acommon terminal 1253. Thus, it is possible to correct (variations in)output current (programming current) by varying the Vt of the unittransistors 634 in the transistor group 681 c 1, the Vt of the unittransistors 634 in the transistor group 681 c 2, and the Vt of the unittransistors 634 in the transistor group 681 cn.

Although three reference current generator circuits are formedseparately in FIG. 131, this is not restrictive and four or morereference current generator circuits may be formed. They may beconstructed of the transistors 633 a in the transistor group 681 b shownin FIG. 128. By using the configuration in FIG. 128 and controlling(adjusting) the current passed through the transistors 632 a composingcurrent mirrors, it is possible to simultaneously control (adjust) thereference currents Ib1, Ib2, and Ib3 shown in FIG. 130. That is, thetransistors 633 b 1, 633 b 2, and 633 b 3 are controlled as a transistorgroup (see FIG. 131(b)).

FIG. 130 shows a configuration in which a reference current regulatingmeans 651 a is formed or placed for the transistor 633 b 1 and areference current regulating means 651 b is formed or placed for thetransistor 633 b 2. FIG. 132 shows a configuration in which a sourceterminal is shared by the transistors 633 b 1 and 633 b 2 and areference current regulating means 651 is formed or placed. Thereference currents Ib1 and Ib2 are controlled (adjusted) to vary by thecurrent regulating means 651. The programming current outputted from theunit transistors 634 varies in proportion to changes in the referencecurrents Ib1 and Ib2. The transistor 633 b 1 and transistor 633 b 2 areconnected in the same manner as the transistors 633 b in the transistorgroups 681 c shown in FIG. 123.

The reference currents Ib1 and Ib2 are controlled or adjusted by areference current regulating means 651 (which, needless to say, is notlimited to a variable regulator, and may be an electronic regulator).The unit transistors 634 in each transistor group 681 c form currentmirror circuits in conjunction with the transistors 633 b (633 b 1 and633 b 2). The reference currents Ib1 and Ib2 define the magnitude ofoutput current from the unit transistors 634.

With the configuration shown in FIG. 129, the reference current Ib1 isused to adjust mainly the gate terminal voltage at point a to apredetermined value and reference current Ib2 is used to adjust mainlythe gate terminal voltage at point b to a predetermined value. Thereference currents Ib1 and Ib2 are basically the same current. Thetransistors 633 b 1 and 633 b 2, which are formed close to each other,have an equal transistor Vt.

Thus, the transistor 633 b 1 and transistor 633 b 2 share a gateterminal and the voltages at point a and point b are equal.Consequently, voltage is supplied from both sides of the common terminal1253, making the voltage at the common terminal 1253 uniform on left andright sides of the IC chip. Once the voltage at the common terminal 1253is uniform, voltages at the gate terminals of all the unit transistors634 in the transistor groups 681 c become equal. This eliminatesvariations in the programming current outputted from the unittransistors 634 to the source signal lines 18.

In this way, the configuration in FIG. 132 contains two transistors 633b which generate reference current sources. FIG. 133 shows aconfiguration in which gate voltage of a transistor 633 b 2 constitutinga reference current source is applied to the center of the commonterminal 1253 as well.

The reference current generator circuit 1 delivers the reference currentIb1 and the reference current generator circuit 2 delivers the referencecurrent Ib2. A reference current generator circuit 3 delivers referencecurrent Ib3. The reference current Ib1, reference current Ib2, andreference current Ib3 have the same current value. The referencecurrents are controlled or adjusted by a reference current regulatingmeans 651 (which, needless to say, is not limited to a variableregulator, and may be an electronic regulator).

Although three reference current generator circuits are formedseparately in FIG. 133, this is not restrictive and four or morereference current generator circuits may be formed.

Incidentally, in the configurations in FIGS. 126, 127, 128, etc.,transistors which pass reference currents are placed or formed on bothsides of the gate wiring 1261. However, the present invention is notlimited to this. Needless to say, a constant voltage may be applieddirectly to the gate wiring 1261 instead of placing transistors. Theabove items also apply to other examples of the present invention.

In the above examples, current-based or voltage-based delivery iscarried out mainly in a single-stage configuration. However, the presentinvention is not limited to this. Needless to say, as shown in FIG. 146,for example, the present invention is also applicable to a multi-stageconfiguration shown in FIG. 68.

In FIG. 147, transistors 631 a and 631 b are formed or placed on bothends (on or around the left and right ends of an IC chip) of thetransistor group 681 a. Also, variable resistors 651 are formed orplaced as adjusting means of reference currents. Incidentally, thereference currents Ia1 and Ia2 maybe fixed. Needless to say, thereference currents Ia1 and Ia2 may be equal.

By adjusting the reference currents Ia1 and Ia2 by the reference currentregulating means 651, it is possible to adjust output current Ib of thetransistors 632 in the transistor group 681 a. The current Ib isdelivered to a transistor 632 b, causing a current to flow through thetransistors 633 a in the transistor groups 681 b which form currentmirror circuits and thereby determining the output current of the unittransistors 634. Other items are the same as in FIG. 68 and the like,and thus description thereof will be omitted.

Although it has been stated that the magnitudes of the referencecurrents which flow through the transistors placed on both sides of thechip are adjusted by electronic regulators or the like, the presentinvention is not limited to this. For example, this can be accomplishedby trimming reference current adjustment resistors Rm as illustrated inFIG. 165. That is, resistance values are increased by trimming theresistors Rm by the laser light 1502 emitted from the laser device 1501.Increasing the resistance values of the resistors Rm changes thereference currents Ia. By trimming resistors Rm1 or Rm2, it is possibleto adjust the reference currents Ia1 and Ia2, respectively.

Preferably, the currents generated by the transistors composing currentmirror circuits are delivered by a plurality of transistors. Transistorsformed in an IC chip 14 have variations in characteristics. To suppressvariations in transistor characteristics, the size of the transistorscan be increased. However, if transistor size is increased, the currentmirror ratios of the current mirror circuits may deviate. To solve thisproblem, it is advisable to make current- or voltage-based deliveryusing a plurality of transistors. The use of multiple transistorsdecreases overall variations even if there are variations in thecharacteristics of individual transistors. This also improves theaccuracy of current mirror ratios. All in all, the area of the IC chipis reduced as well. FIG. 156 shows an example. Incidentally, the aboveitems apply to both current-based or voltage-based multi-stage deliveryand current-based or voltage-based single-stage delivery.

In FIG. 156, the transistor group 681 a and transistor groups 681 bcompose current mirror circuits. The transistor group 681 a consists ofa plurality of transistors 632 b. On the other hand, each of thetransistor groups 681 b consists of a plurality of transistors 633 a.Similarly, each of the transistor groups 631 c consists of a pluralityof transistors 633 c.

The transistor group 681 b 1, transistor group 681 b 2, transistor group681 b 3, transistor group 681 b 4, and so on are composed of the samenumber of transistors 633 a. Also, the total area of the transistors 633a is (approximately) equal among the transistor groups 681 b (where thetotal area is the W and L sizes of the transistors 633 a in eachtransistor group 681 b multiplied by the number of the transistors 633a). The same applies to the transistor groups 681 c.

Let Sc denote the total area of the transistors 633 b in each transistorgroup 681 c (where the total area is the W and L sizes of thetransistors 633 b in each transistor group 681 c multiplied by thenumber of the transistors 633 b). Also, let Sb dente the total area ofthe transistors 633 a in each transistor group 681 b (where the totalarea is the W and L sizes of the transistors 633 a in each transistorgroup 681 b multiplied by the number of the transistors 633 a). Also,let Sa dente the total area of the transistors 632 b in each transistorgroup 681 a (where the total area is the W and L sizes of thetransistors 632 b in the transistor group 681 a multiplied by the numberof the transistors 632 b). Also, let Sd dente the total area of the unittransistors 634 per output.

Preferably, the total area Sc and the total area Sb are approximatelyequal. Also, it is preferably that the transistors 633 a composing eachtransistor group 681 b and the transistors 633 b composing eachtransistor group 681 c are equal in number. However, considering layoutconstraints on the IC chip 14, the transistors 633 a composing eachtransistor group 681 b may be made smaller in number and larger in sizethan the transistors 433 b composing each transistor group 681 c. Anexample of the above configuration is shown in FIG. 157. The transistorgroup 681 a consists of a plurality of transistors 632 b. The transistorgroup 681 a and transistors 633 a compose a current mirror circuit. Thetransistors 633 a generates current Ic. One transistor 633 a drives aplurality of transistors 633 b in a transistor group 681 c (the currentIc from the single transistor 633 a is shunted to the plurality oftransistors 633 b . Generally, the number of transistors 633 acorresponds to the number of output circuits. For example, in a QCIF+panel, there are 176 transistors 633 a in each of R, G, and B circuits.

The relationship between the total area Sd and total area Sc iscorrelated with output variations. This correlation is shown in FIG.210. For a variation rate and the like, refer to FIG. 170. The variationrate when total area Sd:total area Sc=2:1 (Sc/Sd=1/2) is taken as 1. Ascan bee seen from FIG. 210, a small Sc/Sd ratio results in a sharpdeterioration in the variation rate. A poor variation rate resultsespecially when Sc/Sd is 1/2 or less. Output variations decrease whenSc/Sd is 1/2 or above. The decrease is gradual. Output variations fallwith in an allowable range when Sc/Sd is around 1/2 or larger. In viewof the above circumstances, it is preferable that 1/2≦Sc/Sd issatisfied. However, a larger Sc means a larger IC chip. Thus, an upperlimit of Sc/Sd=4 should be provided. That is, a relationship 1/2≦Sc/Sd≦4should be satisfied.

Incidentally, A≧B means that A is equal to or larger than B. A>B meansthat A is larger than B. A≦B means that A is equal to or smaller than B.A<B means that A is smaller than B.

Besides, preferably the total area Sd and total area Sc areapproximately equal. Furthermore, preferably the number of the unittransistors 634 per output and the number of the transistors 633 b ineach transistor group 681 c are equal. That is, in the case of 64gradations, there are 63 unit transistors 634 per output. Thus, thereare 63 transistors 633 b in the transistor group 681 c.

Also, preferably the transistor group 681 a, transistor groups 681 b,and the transistor groups 681 c are composed of unit transistors 634whose WL area is within a factor of four. More preferably, they arecomposed of unit transistors 484 whose WL area is within a factor oftwo. Even more preferably, they are composed of unit transistors 484 ofthe same size. That is, current mirror circuits and the output currentcircuit 704 are composed of transistors of approximately the same size.

The total area Sa should be larger than the total area Sb. Preferably, arelationship 200 Sb≧Sa≧4 Sb is satisfied. Also, the total area Sa of thetransistors 663 a composing all the transistor groups 681 b should beapproximately equal to Sa.

Incidentally, as illustrated in FIG. 164, the transistor 632 a whichforms current mirror circuits in conjunction with the transistor groups681 b does not need to be included in the transistor group 681 a (seeFIG. 156).

In the configuration in FIGS. 126, 127, 128, 147, or the like,transistors which pass reference currents are placed or formed on bothsides of the gate wiring 1261. FIG. 158 shows an example in which thisconfiguration (scheme) is applied to the configuration in FIG. 157. InFIG. 158, transistor groups 681 a 1 and 681 a 2 are placed or formed onboth sides of the gate wiring 1261. Other items are the same as in FIG.126, 127, 128, 147, etc. and thus description thereof will be omitted.

In the configuration shown in FIGS. 126, 127, 128, 147, 158, etc., atransistor or transistor group is placed at each end of the gate wiring1261. Thus, a total of two transistors or two transistor groups areplaced at both ends of the gate wiring 1261. However, the presentinvention is not limited to this. As illustrated in FIG. 159, atransistor or transistor group may be placed at the center or otherlocation of the gate wiring 1261. Three transistor groups 681 a areformed in FIG. 159. The present invention is characterized in that aplurality of transistors or transistor groups 681 are formed on the gatewiring 1261. The use of multiple transistors or transistor groups makesit possible to reduce the impedance of the gate wiring 1261, resultingin improved stability.

To further improve the stability, it is preferable to form or place acapacitor 1601 on the gate wiring 1261 as illustrated in FIG. 160.Alternatively, the capacitor 1601 may be formed in the IC chip 14 orsource driver circuit 14 or placed or mounted outside the chip as anexternal capacitor of the IC 14. When mounting the capacitor 1601externally, a capacitor connection terminal is placed on an IC chipterminal.

The above example is configured to pass a reference current, copy thereference current using a current mirror circuit, and transmit thereference current to the unit transistor 634 in the final stage. Whenthe image display is black display (complete black raster), current doesnot flow through any unit transistor 634 because every switch 641 isopen. Thus, 0 (A) current flows through the source signal line 18,consuming no power.

However, even during black raster display, reference currents flow.Examples include the current Ib and Ic in FIG. 161. They become reactivecurrents. Reference currents flow efficiently if configured to flowduring current programming. Thus, the flow of reference current islimited during vertical and horizontal blanking periods of images. Also,the flow of reference current is limited during wait periods.

To prevent reference current from flowing, a sleep switch 1611 can beopened as shown in FIG. 161. The sleep switch 1611 is an analog switch.The analog switch is formed in the source driver circuit or sourcedriver IC 14. Of course, the sleep switch 1611 may be placed outside theIC 14 and controlled.

When the sleep switch 1611 is turned off, the reference current Ib stopsflowing. Consequently, current does not flow through the transistors 633a in a transistor group 681 a 1, and the reference current Ic is alsoreduced to 0 A. Thus, current does not flow through the transistors 633b in a transistor group 681 c either. This improves power efficiency.

FIG. 162 is a timing chart. A blanking signal is generated in sync witha horizontal synchronization signal HD. The period when the blankingsignal is high corresponds to a blanking period. When the blankingsignal is low, a video signal is being applied. The sleep switch 1611 isoff (open) when the blanking signal is low, and on when the signal ishigh.

During a blanking period A when the sleep switch 1611 is off, referencecurrent does not flow. During a period D when the sleep switch 1611 ison, the reference current flows.

Incidentally, on/off control of the sleep switch 1611 may be performedaccording to image data. For example, when all image data in a pixel rowis black image data (for a period of 1 H, the programming currentsoutputted to all source signal lines 18 are 0), the sleep switch 1611 isturned off to stop reference currents (Ic, Ib, etc.) from flowing. Also,asleep switch may be formed or placed for each source signal line and besubjected to on/off control. For example, when an odd-numbered sourcesignal line 18 is in black display mode (vertical black stripe display),the corresponding sleep switch is turned off.

With the configuration shown in FIG. 124, the reference current Ib flowsthrough the transistor 633 during a video period. The switches 641 areturned on and off according to image data and current flows through theappropriate unit transistors 634. All the switches 641 are open duringblack raster display. Even if the switches 641 are open, since thereference current Ib flows through the transistor 633, the unittransistors 634 try to pass current. This lowers inter-channel voltage(Vsd) of the unit transistors 634 (eliminates potential differencebetween source potential and drain potential). The potential of the gatewiring 1261 of the unit transistors 634 also drops at the same time.When an image changes from black raster to white raster, the switches641 are turned on, developing the voltage Vsd in the unit transistors634. There is a parasitic capacitance between the gate wiring 1261 andinternal wiring 643 (the source signal line 18).

The parasitic capacitance between the gate wiring 1261 and internalwiring 643 (the source signal line 18) in conjunction with the Vsd inthe unit transistors 634 causes potential fluctuations in the gatewiring 1261. The potential fluctuations cause changes to the outputcurrent of the unit transistors 634. The changes in the output currentproduce horizontal streaks and the like in images. The horizontalstreaks appear where the images change from white display to blackdisplay or from black display to white display.

FIG. 151 illustrates potential fluctuations in the gate wiring 1261.Linking occurs at image change points (where the images change fromwhite display to black display, from black display to white display,etc.).

FIG. 152 shows a method of solving this problem. Resistors Rare formedor placed in the selector switches 641. Specifically, sizes of theanalog switches 641 are changed instead of forming the resistors R.Thus, FIG. 152 is an equivalent circuit diagram of the switches 641.

The resistors in the switches 641 are designed to satisfy the followingrelations.R1<R2<R3<R4<R5<R6

D0 is provided by 1 unit transistor 634. D1 is provided by 2 unittransistors 634. D2 is provided by 4 unit transistors 634. D3 isprovided by 8 unit transistors 634. D4 is provided by 16 unittransistors 634. D5 is provided by 32 unit transistors 634. Thus, thecurrent flowing through the switches 641 increases with changes from D0to D5. It is also necessary to lower the on-resistance of the switchesaccordingly. On the other hand, it is also necessary to reduce linkingas illustrated in FIG. 151. The configuration shown in FIG. 152 makes itpossible to reduce linking and adjust the on-resistance of the switches.

The linking of the gate wiring 1261 in FIG. 151 is caused by existenceof an image which turns off all the unit transistors 634 and flow of thereference current Ib while all the unit transistors 634 are off (seeFIG. 153 and the like). For the above reasons, the gate wiring of theunit transistors 634 is prone to potential fluctuations.

FIG. 127 and the like show configuration which contain multi-stagecurrent mirror connections. FIGS. 129 to 133 show single-stageconfigurations. The problem of swinging gate wiring 1261 has beendescribed with reference to FIG. 151. The swing is influenced by thepower supply voltage of the source driver IC 14 because the power supplyvoltage swings to a maximum voltage. FIG. 211 shows a ratio of potentialfluctuations of the gate wiring based on the value obtained when thepower supply voltage of the source driver IC 14 is 1.8 V. Thefluctuation ratio increases with increases in the power supply voltageof the source driver IC 14. An allowable range of fluctuation ratio isapproximately 3. A higher fluctuation ratio will cause horizontalcross-talk. The fluctuation ratio with respect to the power supplyvoltage tends to increase when the power supply voltage of the IC is 10to 12 V or higher. Thus, the power supply voltage of the source driverIC 14 should be 12 V or less.

On the other hand, in order for a driver transistor 11 a switch fromwhite-display current to black-display current, it is necessary to makea certain amplitude change to the potential of the source signal line18. The required range of amplitude change is 2.5 V or more. It is lowerthan the power supply voltage because the output voltage of the sourcesignal line 18 cannot exceed the power supply voltage.

Thus, the power supply voltage of the source driver IC 14 should be from2.5 V to 12 V (both inclusive). The use of this range makes it possibleto keep fluctuations in the gate wiring 1261 within a stipulated range,eliminate horizontal cross-talk, and thus achieve proper image display.

Wiring resistance of the gate wiring 1261 also presents a problem. InFIG. 215, the wiring resistance (Ω) of the gate wiring 1261 is theresistance of the wiring throughout its length from transistor 633 b 1to transistor 633 b 2 or the resistance of the gate wiring throughoutits length. The magnitude of a transient phenomenon as shown in FIG. 151depends on one horizontal scanning period (1 H) as well because theshorter the period of 1 H, the larger the impact of the transientphenomenon. A larger wiring resistance (Ω) makes a transient phenomenonas shown in FIG. 151 easier to occur. This phenomenon poses a problemespecially for the configurations of single-stage current-mirrorconnections shown in FIGS. 129 to 133, and 215 to 220 in which the gatewiring 1261 is long and connected with a large number of unittransistors 634.

FIG. 212 is a graph in which the horizontal axis represents the product(R·T) of wiring resistance (Ω) of the gate wiring 1261 and 1-H period T(sec) while the vertical axis represents a fluctuation ratio. Thefluctuation ratio is taken as 1 when R·T=100. As can be seen from FIG.212, fluctuation ratio tends to grow larger when R·T is 5 or less.Fluctuation ratio also tends to grow larger when R·T is 1000 or more.Thus, it is preferable that R·T is from 5 to 100 (both inclusive).

Another method of solving this problem is shown in FIG. 153. In FIG.153, the unit transistors 1531 which pass current steadily are formed orplaced. These transistors 1531 are referred to as steady-statetransistors 1531.

The steady-state transistors 1531 pass current Is constantly while thereference current Ib is flowing. Thus, they do not depend on themagnitudes of the programming current Iw. The flow of the current Isreduces potential fluctuations of the gate wiring 1261. Preferably, thecurrent Is is from 2 to 8 times (both inclusive) as large as the currentflowing through the unit transistors 634. The steady-state transistors1531 are constructed of multiple transistors with the same WL as theunit transistors 634. Also, preferably the steady-state transistors 1531are formed at a location farthest from the transistor 633 which passesthe reference current Ib.

Although it has been stated with reference to FIG. 153 that multiplesteady-state transistors 1531 are formed, the present invention is notlimited to this. A single steady-state transistor 1531 may be formed asshown in FIG. 155. Also, steady-state transistors 1531 may be formed atmultiple locations as shown in FIG. 154. In FIG. 154, one steady-statetransistor 1531 a is formed near the transistor 633 and foursteady-state transistors 1531 b are formed at a location farthest fromthe transistor 633.

In FIG. 154, a switch S1 is formed for the steady-state transistors 1531b. The switch S1 is turned on and off according to image data (D0 toD5). In the case of black raster image data (including image data closeto black raster (higher-order bits of D are 0)), output of a NOR circuit1541 goes high, the switch S1 turns on, and a current Is2 flows throughthe steady-state transistors 1531. Otherwise, the switch S1 remains offand current does not flow through the steady-state transistors 1531.This configuration can reduce power consumption.

FIG. 163 shows a configuration which includes both the steady-statetransistors 1531 and sleep switch 1611. Thus, needless to say, what hasbeen described herein can be used in combination.

Dummy transistor groups 681 c are formed or placed on outer sides of thetransistor groups 681 c 1 and 681 cn located on both ends of the chipIC. Preferably, at least two dummy transistor groups 681 c are formed onthe left and right (outermost sides) of the chip IC. More preferably,three to six circuits (both inclusive) are formed. Without dummytransistor groups 681 c, a diffusion process or etching process duringproduction of the IC will cause the unit transistors 634 in outertransistor groups 681 c to differ in Vt from those in the center of theIC chip 14. Difference in the Vt will cause variations in the outputcurrent (programming current) of the unit transistors 634.

FIGS. 129 to 133 are block diagrams of a driver IC with a single-stagecurrent mirror configuration. The single-stage configuration will bedescribed further. FIG. 215 shows a single-stage driver circuitconfiguration. The transistor groups 681 c in FIG. 215 correspond to anoutput stage configuration consisting of the unit transistors 634 shownin FIG. 214 (see also FIGS. 129 to 133).

The transistor 632 b and two transistors 633 a compose a current mirrorcircuit. The transistor 633 a 1 and transistor 633 a 2 are of the samesize. Thus, current Ic passed by the transistor 633 a 1 and current Icpassed by the transistor 633 a 2 are identical.

In FIG. 214, the transistor groups 681 c consisting of unit transistors634 compose current mirror circuits together with the transistor 633 b 1and transistor 633 b 2. There are variations in the output current ofthe transistor groups 681 c. However, transistor groups 681 whichcompose a current mirror circuit in close vicinity to each other havetheir output current controlled accurately. The transistor 633 b 1 andtransistor group 681 c 1 compose a current mirror circuit in closevicinity to each. Also, The transistor 633 b 2 and transistor group 681cn compose a current mirror circuit in close vicinity to each. If thecurrent flowing through the transistor 633 b 1 and the current flowingthrough the transistor 633 b 2 are equal, the output current of thetransistor group 681 c 1 and the output current of the transistor group681 cn are equal. If the current is generated in each IC chipaccurately, the output currents of the transistor groups 681 c at bothends of the output stage are equal in any IC chip. Thus, even if ICchips are cascaded, seams between ICs can be made inconspicuous.

As is the case with FIG. 123, a plurality of transistors 633 b may beprovided to form a transistor group 681 b 1 and transistor 681 b 2.Also, a plurality of transistors 633 a may be provided to form atransistor group 681 a as in FIG. 123.

Although it has been stated that the transistor 632 b current isspecified by the resistance R1, this is not restrictive. Electronicregulators 1503 a and 1503 b may be used as shown in FIG. 218. In theconfiguration shown in FIG. 218, the electronic regulators 1503 a and1503 b can be operated independently. Thus, the values of the currentsflowing through the transistors 632 a 1 and 632 a 2 can be changed. Thismakes it possible to adjust the slopes of the output currents in outputstages 681 c on the left and right sides of the chip. Incidentally, itis also possible to provide only one electronic regulator 1503 as shownin FIG. 219 and use it to control two operational amplifiers 722.

The sleep switch 1611 has been described with reference to FIG. 161.Needless to say, a sleep switch may be placed or formed similarly asshown in FIG. 220. In FIGS. 153, 154, 155, and 163, it has been statedthat the steady-state transistors 1531 are formed or placed, and thesteady-state transistors 1531 in FIG. 226(b) may be formed or placed inblock A as illustrated in FIG. 225.

Also, it has been stated with reference to FIG. 160 that the capacitor1601 is connected to the gate wiring 1261 for stability, and it goeswithout saying that the stabilizing capacitor 1601 in FIG. 226(a) may beplaced in the block A in the FIG. 225 as well.

Also, it has been stated with reference to FIG. 165 and the like thatresistors and the like are trimmed for adjustment of current. Similarly,needless to say, the resistor R1 or R2 may be trimmed as illustrated inFIG. 225.

It has been stated with reference to FIG. 210 that there are conditionsfor the area in which the transistor groups 681 are constructed.However, the conditions in FIG. 210 do not apply to the single-stagecurrent mirror configurations in FIGS. 129 to 133 and FIGS. 215 to 220,in which there are a very large number of unit transistors 634. Anoutput stage of a single-stage driver circuit will be describedadditionally below. Incidentally, for ease of explanation, FIGS. 216 and217 will be taken as an example. However, since the description concernsthe number and total area of transistors 633 b as well as the number andtotal area of unit transistors 634, it goes without saying that thedescription applies to other examples as well.

FIGS. 216 and 217, let Sb denote the total area of the transistors 633 bin each transistor group 681 b (where the total area is the W and Lsizes of the transistors 633 b in each transistor group 681 b multipliedby the number of the transistors 633 b). Incidentally, if transistorgroups 681 b are installed on the left and right of the gate wiring 1261as in FIGS. 216 and 217, the area is doubled. If there is one transistoras shown in FIG. 129, Sb equals the area of the transistor 633 b. If thetransistor group 681 b consists of a single transistor 633 b, needlessto say, Sb equals the size of the one transistor 633 b.

Also, let Sc denote the total area of the unit transistors 634 in eachtransistor group 681 c (where the total area is the W and L sizes of thetransistors 634 in each transistor group 681 c multiplied by the numberof the transistors 634). It is assumed that the number of the transistorgroups 681 c is n. In the case of a QCIF+ panel, n is 176 (a referencecurrent circuit is formed for each of R, G, and B).

In FIG. 213, the horizontal axis represents Sc×n/Sb and the verticalaxis represents a fluctuation ratio. The fluctuation ratio in the worstcase is taken as 1. As illustrated in FIG. 213, the fluctuation ratiodeteriorates with increases in Sc×n/Sb. A large value of Sc×n/Sb meansthat the total area of the unit transistors 634 in the transistor groups681 c is larger than the total area of the transistors 633 b in thetransistor groups 681 b when the number n of output terminals isconstant. In that case, the fluctuation ratio is unfavorable.

A small value of Sc×n/Sb means that the total area of the unittransistors 634 in the transistor groups 681 c is smaller than the totalarea of the transistors 633 b in the transistor groups 681 b when thenumber n of output terminals is constant. In that case, the fluctuationratio is small.

An allowable range of fluctuations corresponds to a value of Sc×n/Sb of50 or less. When Sc×n/Sb is 50 or less, the fluctuation ratio fallswithin the allowable range and potential fluctuations of the gate wiring1261 is extremely small. This makes it possible to eliminate horizontalcross-talk, keep output variations within an allowable range, and thusachieve proper image display. It is true that the fluctuation ratiofalls within the allowable range when Sc×n/Sb is 50 or less. However,decreasing Sc×n/Sb to 5 or less has almost no effect. On the contrary,Sb becomes large, increasing the chip area of the IC 14. Thus,preferably Sc×n/Sb to 5 should be from 5 to 50 (both inclusive).

Also, placement of unit transistors 634 in the transistor groups 681 chas consideration.

The transistor groups 681 c should be placed orderly. Any dropout of aunit transistor 634 will make the characteristics of the unittransistors 634 around it different from the characteristics of theother unit transistors 634.

FIG. 134 schematically illustrates an arrangement of the unittransistors 634 in the transistor groups 681 c in the output stage.Sixty-three (63) unit transistors 634 which represent 64 gradations arearranged orderly in a matrix. However, although 64 unit transistors 634could be arranged in 4 rows×16 columns, arrangement of 63 unittransistors 634 produces a vacancy (shaded area). This makes thecharacteristics of the unit transistors 634 a, 634 b, and 634 c aroundthe shaded area different from the characteristics of the other unittransistors 634.

To solve this problem, the present invention forms or places a dummytransistor 1341 in the shaded area. This makes the characteristics ofthe unit transistors 634 a, 634 b, and 634 c coincide with thecharacteristics of the other unit transistors 634. That is, by formingthe dummy transistors 1341, the present invention arranges the unittransistors 634 in a matrix. Also, the unit transistors 634 are arrangedin a matrix without any omission. Also, the unit transistors 634 arearranged axisymmetrically.

Although it has been stated that 63 unit transistors 634 are arranged ineach transistor group 681 c to represent 64 gradations, the presentinvention is not limited to this. The unit transistor 634 may be furthercomposed of a plurality of sub-transistors.

FIG. 135(a) shows the unit transistor 634. FIG. 135(b) shows a unittransistor (single unit) 1351 composed of four sub-transistors 1352. Theunit transistor (single unit) 1351 is designed to be equal in outputcurrent to the unit transistor 634. That is, the unit transistor 634 iscomposed of four sub-transistors 1352. Incidentally, the presentinvention is not limited to a configuration in which the unit transistor634 is composed of four sub-transistors 1325, and is applicable to anyconfiguration in which the unit transistor 634 is composed of multiplesub-transistors 1352. However, the sub-transistors 1352 are designed tobe of the same size or to produce the same output current.

In FIG. 135, reference character S denotes the source terminal of atransistor, G denotes the gate terminal of the transistor, and D denotesthe drain terminal of the transistor. In FIG. 135(b), thesub-transistors 1352 are oriented in the same direction. In FIG. 135(c),the sub-transistors 1352 are oriented differently between differentrows. In FIG. 135(d), the sub-transistors 1352 are oriented differentlybetween different columns and arranged symmetrically about a point. Allthe arrangements in FIGS. 135(b), 135(c), and 135(d) have regularities.

Changes in the formation direction of the unit transistors 634 orsub-transistors 1352 often change their characteristics. For example, inFIG. 135(c), the unit transistor 634 a and sub-transistor 1352 b producedifferent output currents even if an equal voltage is applied to theirgate terminals. However, in FIG. 135(c), sub-transistors 1352 withdifferent characteristics are formed in equal numbers. This reducesvariations in the transistor (unit) as a whole. If the orientations ofunit transistors 634 or sub-transistors 1352 with different formationdirections are changed, differences in characteristics will complementeach other, resulting in reduced variations in the transistor (singleunit). Needless to say, the above items also apply to the arrangement inFIG. 135(d).

Thus, as illustrated in FIG. 136 and the like, by changing theorientations of unit transistors 634, it is possible to cause thecharacteristics of the unit transistors 634 formed in the verticaldirection and the characteristics of the unit transistors 634 formed inthe horizontal direction to complement each other in the transistorgroups 681 c as a whole, resulting in reduced variations in the transistor groups 681 c as a whole.

FIG. 136 shows an example in which the unit transistors 634 are orienteddifferently between different columns within each transistor groups 681c. FIG. 137 shows an example in which the unit transistors 634 areoriented differently between different rows within each transistorgroups 681 c. FIG. 138 shows an example in which the unit transistors634 are oriented differently between different rows as well as betweendifferent columns within each transistor group 681 c. Incidentally,these requirements are also observed when forming or placing a dummytransistor 1341.

The above examples involve constructing or forming unit transistors ofthe same size or same current output in the transistor groups 681 c (seeFIG. 139(b)). However, the present invention is not limited to this. Aconfiguration illustrated in FIG. 139(a) may also be used as follows. Asingle-unit unit transistor 634 a is connected (formed) for the 0th bit(switch 641 a). A 2-unit unit transistor 634 b is connected (formed) forthe 1st bit (switch 641 b). A 4-unit unit transistor 634 c is connected(formed) for the 2nd bit (switch 641 c). An 8-unit unit transistor 634 dis connected (formed) for the 3rd bit (switch 641 d). A 16-unit unittransistor 634 a is connected (formed) for the 4th bit (not shown). A32-unit unit transistor 634 a is connected (formed) for the 5th bit (notshown). Incidentally, a 16-unit unit transistor, for example, is atransistor which outputs current equivalent to the current outputted by16 unit transistors 634.

An n-unit (n is an integer) unit transistor can be formed easily bychanging the channel width W proportionally (while keeping the channellength L constant). Actually, however, doubling the channel width Woften does not double the output current. Thus, the channel width W isdetermined experimentally by actually building transistors. According tothe present invention, however, even if the channel width W deviatesmore or less from proportionality, it is assumed that the channel widthW is proportional.

Reference current circuits will be described below. Output currentcircuits 704 are formed (placed) individually for R, G, and B. The RGBoutput current circuits 704R, 704G, and 704B are placed in closevicinity. Also, a reference current INL in a low-current region in FIG.73 and reference current INH in a low-current region in FIG. 74 areadjusted to each color (R, G, and B) (see also FIG. 79).

Thus, an output current circuit 704R for R is equipped with a regulator(or an electronic regulator for voltage output or current output) 651RLto adjust the reference current INL in the low-current region and aregulator (or an electronic regulator for voltage output or currentoutput) 651RH to adjust the reference current INH in the high-currentregion. Similarly, an output current circuit 704G for G is equipped witha regulator (or an electronic regulator for voltage output or currentoutput) 651GL to adjust the reference current INL in the low-currentregion and a regulator (or an electronic regulator for voltage output orcurrent output) 651GH to adjust the reference current INH in thehigh-current region. Also, an output current circuit 704B for B isequipped with a regulator (or an electronic regulator for voltage outputor current output) 651BL to adjust the reference current INL in thelow-current region and a regulator (or an electronic regulator forvoltage output or current output) 651BH to adjust the reference currentINH in the high-current region.

Preferably, the regulators 651 and the like should be capable ofaccommodating temperature changes to compensate for temperaturecharacteristics of the EL element 15. Needless to say, if there are twoor more breakpoints in gamma characteristics shown in FIG. 79, three ormore electronic regulators or resistors maybe provided to adjust thereference currents for the different colors.

Output pads 761 are formed or placed on the output terminals of the ICchip. They are connected with the source signal lines 18 of the displaypanel. A bump is formed on the output pads 761 by a plating technique orball bonding technique. The bump should be 10 to 40 μm high (bothinclusive).

The bumps and the source signal lines 18 are connected electrically viaa conductive bonding layer (not shown). The conductive bonding layer ismade of an epoxy or phenolic base resin mixed with flakes of silver(Ag), gold (Au), nickel (Ni), carbon (C), tin oxide (SnO2), and thelike, or made of an ultraviolet curing resin. The conductive bondinglayer is formed on the bump by a transfer or other technique. Also, thebumps and the source signal lines 18 are bonded by thermocompressionusing an ACF resin. Incidentally, the techniques for connecting thebumps or output pads 761 with the source signal lines 18 are not limitedto those described above. Besides, a film carrier technique may be usedinstead of mounting the IC 14 on the array board. Also, polyimide filmsand the like may be used for connection with the source signal lines 18and the like.

Referring to FIG. 69, inputted 4-bit current control data (DI) isdecoded by a 4-bit decoder circuit 692 (needless to say, a 6-bit decodercircuit is used if there are 64 divisions. For ease of explanation, itis assumed here that 4-bit data is used). Decoder output is boosted fromlogic level voltage value to analog level voltage value by a levelshifter circuit 693 and is entered into the analog switch 641.

Main components of an electronic regulator circuit are a fixed resistorR0 (691 a) and 16 unit registers r (691 b). Output from the decodercircuit 692 is connected to one of 16 analog switches 641 and designedto determine the resistance value of the electronic regulator by theoutput from the decoder circuit 692. For example, if an output of thedecoder circuit 692 is 4, the resistance value of the electronicregulator is R0+5r. The resistance value of the electronic regulatoracts as a load on the first-stage current source 631 and is pulled up toan analog power supply AVdd. Thus, changes in the resistance value ofthe electronic regulator cause changes to the current value of thefirst-stage current source 631. This in turn causes changes to thecurrent value of the second-stage current source 632, consequentlycausing changes to the current value of the third-stage current source633. The output current of the driver IC is controlled in this way.

Incidentally, although it has been assumed for the sake of illustrationthat 4-bit data is used for current value control, this is notrestrictive. Needless to say, the larger the bit count, the larger thenumber of steps of current. Also, although it has been stated that themulti-stage current mirrors have a three-stage configuration, needlessto say, this is not restrictive and any number of stages may be used.

Besides, to deal with the problem of changes in emission brightness ofthe EL element caused by temperature changes, preferably the electronicregulator circuit is equipped with an external resistor 691 a whoseresistance changes with temperature. FIGS. 33 and 35 and the likexternal resistors whose resistance changes with temperature include, forexample, thermistors, posistors, etc. Generally, light-emitting elementswhose brightness varies with the current flowing through themselves havetemperature dependence and their emission brightness varies withtemperature even if a current of the same value is passed through them.By attaching an external resistor 691 a whose resistance changes withtemperature to an electronic regulator, it is possible to vary thecurrent value of constant-current output with temperature and keep theemission brightness constant even if the temperature changes.

Preferably, the multi-stage current mirror circuits are divided intothree systems for red (R), green (G), and blue (B). Generally, organicEL or other current-driven light-emitting elements have differentemission characteristics among R, G, and B. Thus, to obtain the samebrightness among R, G, and B, the currents passed through thelight-emitting elements should be adjusted separately for R, G, and B.Also, current-driven light-emitting elements such as for organic ELdisplay panel have different temperature characteristics among R, G, andB. Thus, characteristics of auxiliary elements such as thermistorsformed or placed to compensate for temperature characteristics shouldalso be adjusted separately for R, G, and B.

Since the multi-stage current mirror circuits are divided into threesystems for red (R), green (G), and blue (B), the present inventionmakes it possible to adjust emission characteristics and temperaturecharacteristics separately for R, G, and B, and thereby obtain anoptimum white balance.

As described earlier, in the case of current driving, only a smallcurrent is written into pixels during black display. Consequently, ifthe source signal lines 18 or the like have parasitic capacitance,current cannot be written into the pixels 16 sufficiently during onehorizontal scanning period (1 H). Generally, in current-drivenlight-emitting elements, black-level current is as weak as a few nA, andthus it is difficult to drive parasitic capacitance (load capacitance ofwiring) which is assumed to measure tens of pF using the signal value ofthe black-level current. To solve this problem, it is useful to equalizethe black-level current in the pixel transistors 11 a (basically, thetransistors 11 a are off) with the potential level of the source signallines 18 by applying a precharge voltage before writing image data intothe source signal lines 18. In order to form (create) the prechargevoltage, it is useful to output the black level at a constant voltage bydecoding higher order bits of image data.

FIG. 70 shows an example of a current-output type source driver circuit(IC) 14 equipped with a precharge function according to the presentinvention. FIG. 70 shows a case in which the precharge function isprovided in the output stage of a 6-bit constant-current output circuit.In FIG. 70, a precharge control signal is constituted so that it decodesthe case where the higher order three bits D3, D4, and D5 in image dataD0 to D5 are all zero by a NOR circuit 702, takes an AND circuit 703with an output from a counter circuit 701 of a dot clock CLK with areset function based on a horizontal synchronization signal HD, andthereby outputs a black level voltage Vp for a fixed period. In othercases, an output current from the current output stage 704 describedwith reference to FIG. 68, etc. is applied to the source signal lines 18(programming current Iw is drawn from the source signal lines 18). Whenthe image data is composed of the 0th to 7th gradations close to theblack level, by writing a voltage which corresponds to the black levelonly for a fixed period at the beginning of a horizontal period, theabove configuration reduces the burden of current driving and makes upfor insufficient writing. Incidentally, it is assumed that the 0thgradation corresponds to a completely black display while the 63rdgradation corresponds to a completely white display (in the case of64-gradation display).

Preferably, gradations for which precharging is performed should belimited to a black display region. Specifically, precharging isperformed by selecting gradations in a black region (low brightnessregion, in which only a small (weak) write current flows in the case ofcurrent driving) from write image data (selective precharging). Ifprecharging is performed over the entire range of gradations, brightnesslowers (a target brightness is not reached) in a white display region.Also, vertical streaks may be displayed in some cases.

Preferably, selective precharging is performed for ⅛ of all thegradations beginning with the 0th gradation (e.g., in the case of 64gradations, image data is written after precharging for the 0th to 7thgradations). More preferably, selective precharging is performed for1/16 of all the gradations beginning with the 0th gradation (e.g., inthe case of 64 gradations, image data is written after precharging forthe 0th to 3rd gradations).

A method which performs precharging by detecting only the 0th gradationis also effective in enhancing contrast, especially in black display. Itachieves an extremely good black display. The problem is that the screenappears whitish in hue when the entire screen displays the 1st andsecond gradations. Thus, selective precharging is performed in apredetermined range: ⅛ of all the gradations beginning with the 0thgradation. The method of performing precharging by extracting only the0th gradation causes little harm to image display. Thus, it is mostpreferable to adopt this method as a precharging technique.

Incidentally, it is also useful to vary the precharge voltage andgradation range among R, G, and B because emission start voltage andemission brightness of EL elements 15 vary among R, G, and B. Forexample, selective precharging is performed for ⅛ of all the gradationsbeginning with the 0th gradation (e.g., in the case of 64 gradations,image data is written after precharging for the 01th to 7th gradations)in the case of R. In the case of other colors (G and B), selectiveprecharging is performed for 1/16 of all the gradations beginning withthe 0th gradation (e.g., in the case of 64 gradations, image data iswritten after precharging for the 0th to 3rd gradations). Regarding theprecharge voltage, if 7 V is written into the source signal lines 18 forR, 7.5 V is written into the source signal lines 18 for the other colors(G and B). Optimum precharge voltage often varies with the productionlot of the EL display panel. Thus, preferably precharge voltage isadjustable with an external regulator or the like. Such a regulatorcircuit can be also implemented easily using an electronic regulatorcircuit.

Incidentally, it is preferable that the precharge voltage is not higherthan the anode voltage Vdd minus 0.5 V and within the anode voltage Vddminus 2.5 V in FIG. 1.

Even with methods which perform precharging only for the 0th gradation,it is useful to perform precharging selecting one or two colors fromamong R, G, and B. This will cause less harm to image display.

It is preferable to provide several modes which can be switched bycommand: including a 0th mode in which no precharging is performed,first mode in which precharging is performed only for the 0th gradation,second mode in which precharging is performed in the range of the 0th to3rd gradations, third mode in which precharging is performed in therange of the 0th to 7th gradations, and fourth mode in which prechargingis performed in the entire range of gradations and the like. These modescan be implemented easily by constructing (designing) a logic circuit inthe source driver circuit (IC) 14.

FIG. 75 is a diagram showing a concrete configuration of a selectiveprecharging circuit.

Reference character PV denotes an input terminal of precharge voltage.Separate precharge voltages are set for R, G, and B by external inputsor by an electronic regulator circuit. Incidentally, although it hasbeen stated that separate precharge voltages are set for R, G, and B,this is not restrictive. Precharge voltages may be common to R, G, and Bbecause they are correlated with the Vt of the driver transistors 11 aof the pixels 16, which do not differ among R, G, and B. If the W/Lratio and the like of the driver transistors 11 a of the pixels 16 arevaried (designed differently) among R, G, and B, preferably theprecharge voltage is adjusted to the different designs. For example, alarger channel length L of the driver transistor 11 a lowers diodecharacteristics of the transistor 11 a and increases the source-drain(SD) voltage. Thus, the precharge voltage should be set lower than thesource potential (Vdd).

The precharge voltage PV is fed to an analog switch 731. To reduceon-resistance, the W (channel width) of the analog switch 731 should be10 μm or above. However, it is set to 100 μm or below because too largeW will increase parasitic capacitance as well. More preferably, thechannel width W should be between 15 μm and 60 μm (both inclusive). Theabove items also apply to the analog switch 731 in the switch 641b inFIG. 75 and to the analog switch 731 in FIG. 73.

The switch 641 a is controlled by a precharge enable (PEN) signal,selective precharging (PSL) signal, and the higher order three bits (H5,H4, and H3) of the logic signal in FIG. 74. The higher order three bits(H5, H4, and H3) of the logic signal are cited because selectiveprecharging is performed when they are “0.” That is, precharging isperformed selectively when the lower order three bits are “1” (from the0th to the 7th gradation).

Incidentally, although selective precharging may be performed for fixedgradations such as only the 0th gradation or a range of the 0th to 7thgradations, it may be performed automatically in any low gradationregion specified (gradation 0 to gradation R1 or gradation “R1-1” inFIG. 79). Specifically, if a low gradation region ranging from gradation0 to gradation R1 is specified, selective precharging will be performedautomatically in this range, and if a low gradation region ranging fromgradation 0 to gradation R2 is specified, selective precharging will beperformed automatically in this range. This control system requires asmaller hardware scale than other systems.

The switch 641 a is turned on or off depending on which of the abovesignals is applied. When the switch 641 a is on, the precharge voltagePV is applied to the source signal line 18. Incidentally, the timeduring which the precharge voltage PV is applied is set by a counter(not shown) formed separately. The counter is configured to be set bycommand. Preferably, the application duration of the precharge voltageis from 1/100 to ⅕ of one horizontal scanning period (1 H) bothinclusive. For example, if 1 H is 100 μsec, the application durationshould be from 1 μsec to 20 μsec (from 1/100 to ⅕ of 1 H) bothinclusive. More preferably, it should be from 2 μsec to 10 μsec (from2/100 to 1/10 of 1 H) both inclusive.

FIG. 173 shows a variation of FIG. 70 or 75. It shows a prechargecircuit which determines whether to perform precharging according toinput image data and controls precharging. For example, the prechargecircuit can make a setting so as to perform precharging when image datacontains only the 0th gradation, perform precharging when image datacontains only the 0th and 1st gradations, or always perform prechargingwhen the 0th gradation occurs and perform precharging when the 1stgradation occurs consecutively for or beyond a predetermined number oftimes.

FIG. 173 shows an example of a current-output type source driver circuit(IC) 14 equipped with a precharge function according to the presentinvention.

FIG. 173 shows a case in which the precharge function is provided in theoutput stage of a 6-bit constant-current output circuit. In FIG. 173, acoincidence circuit 1731 performs decoding according to image data D0 toD5 and determines whether to perform precharging using inputs in an RENterminal and dot clock CLK terminal equipped with a reset function whichis based on a horizontal synchronization signal HD. The coincidencecircuit 1731 has a memory and retains results of precharging in relationto image data for a few Hs or a few fields (frames). Also, it hascapabilities to control precharging by determining whether to performprecharging, based on the retained data. For example, the coincidencecircuit 1731 can make settings so as to always perform precharging whenthe 0th gradation occurs and perform precharging when the 1st gradationoccurs consecutively for 6 Hs (six horizontal scanning periods) or more.Also, it can make settings so as to always perform precharging when the0th or 1st gradation occurs and perform precharging when the 2ndgradation occurs consecutively for 3 Fs (three frame periods) or more.

The output from the coincidence circuit 1731 and output from the countercircuit 701 are ANDed by the AND circuit 703, and consequently a blacklevel voltage Vp is output for a predetermined period. In other cases,the output current from the current output stage 704 described withreference to FIG. 68 and the like is applied to the source signal lines18 (programming current Iw is drawn from the source signal lines 18).The other part of the configuration is the same as or similar to thoseshown in FIGS. 70, 75, and the like, and thus description thereof willbe omitted. Incidentally, although the precharge voltage is applied topoint A in FIG. 173, needless to say, it may be applied to point B (seealso FIG. 75).

Good results can also be obtained if the duration of application of theprecharge voltage PV is varied using the image data applied to thesource signal lines 18. For example, the application duration may beincreased for the 0th gradation which corresponds to completely blackdisplay, and decreased for the 4th gradation. Also, good results can beobtained if the application duration is specified taking intoconsideration the difference between image data and image data to beapplied 1 H later. For example, when writing a current into the sourcesignal lines to put the pixels in black display mode 1 H after writing acurrent into source signal lines to put the pixels in white displaymode, the precharge time should be increased. This is because a weakcurrent is used for black display. Conversely, when writing a currentinto the source signal lines to put the white pixels in black displaymode 1 H after writing a current into source signal lines to put thepixels in black display mode, the precharge time should be decreased orprecharging should be stopped (no precharging should be done). This isbecause a large current is used for white display.

It is also useful to vary the precharge voltage depending on the imagedata to be applied. This is because a weak current is used for blackdisplay and a large current is used for white display. Thus, theprecharge voltage is raised (in relation to Vdd) in a lower gradationregion (when P-channel transistors are used as pixel transistors 11 a)and the precharge voltage is lowered in a higher gradation region (whenP-channel transistors are used as pixel transistors 11 a).

For ease of understanding, description will be given below mainly withreference to FIG. 75. Needless to say, however, the items describedbelow also apply to precharge circuits shown in FIGS. 70 and 175.

When a programming current open terminal (PO terminal) is “0,” theswitch 1521 is off, disconnecting an IL terminal and IH terminal fromthe source signal line 18 (an Iout terminal is connected with the sourcesignal line 18). Thus, the programming current Iw does not flow throughthe source signal line 18.

When the programming current Iw is applied to the source signal line,the PO terminal is “1,” keeping the switch 1521 on to pass theprogramming current Iw through the source signal line 18. “0” is appliedto the PO terminal to open the switch 1521 when no pixel row in thedisplay area is selected. The unit transistor 634 constantly drawscurrent from the source signal line 18 based on input data (D0 to D5).This current flows into the source signal line 18 from the Vdd terminalof the selected pixel 16 via the transistor 11 a. Thus, when no pixelrow is selected, there is no path for current to flow from the pixel 16to the source signal line 18. A period when no pixel row is selectedoccurs after the time when an arbitrary pixel row is selected until thetime when the next pixel row is selected. Incidentally, the periodduring which no pixel (pixel row) is selected and there is no path forcurrent to flow into (flow out into) the source signal line 18 isreferred to as total non-selection period.

In this state, if the IOUT terminal is connected to the source signalline 18, current flows to activated unit transistors 634 (actually, whatis activated are switches 641 controlled by data from the D0 to D5terminals).

Consequently, charges in the parasitic capacitance of the source signalline 18 are discharged, lowering the potential of the source signal line18 sharply. Then, it takes time for the current normally written intothe source signal line 18 to restore the potential of the source signalline 18.

To solve this problem, the present invention applies “0” to the POterminal during the total non-selection period to turn off the switch1521 in FIG. 75, and thereby disconnect the IOUT terminal from thesource signal line 18.

Consequently, no current flows from the source signal line 18 into theunit transistors 634, and thus the potential of the source signal line18 does not change during the total non-selection period. In this way,by controlling the PO terminal during the total non-selection period anddisconnecting current sources from the source signal line 18, it ispossible to write current properly.

It is useful to add a (proper precharging) capability to stopprecharging when a white display area (area with a certain brightness)(white area) and a black display area (area with brightness below apredetermined level) (black area) coexist in the screen and the ratio ofthe white area to the black area falls within a certain range becausevertical streaks appear in this range. Conversely, precharging may bedone in a range because images may act as noise when they move. Properprecharging can be implemented easily by counting (calculating) pixeldata which correspond to the white area and black area using anarithmetic circuit.

It is also useful to vary precharge control among R, G, and B becauseemission start voltage and emission brightness of EL elements 15 varyamong R, G, and B. For example, a possible method involves stopping orstarting precharging for R when the ratio of a white area with apredetermined brightness to a black area with a predetermined brightnessis 1 to 20 or above and stopping or starting precharging for G and Bwhen the ratio of a white area with a predetermined brightness to ablack area with a predetermined brightness is 1 to 16 or above. It hasbeen shown experimentally and analytically that in an organic EL panel,preferably precharging should be stopped when the ratio of a white areawith a predetermined brightness to a black area with a predeterminedbrightness is 1 to 100 or above (i.e., the black area is at least 100times larger than the white area). More preferably, precharging shouldbe stopped when the ratio of a white area with a predeterminedbrightness to a black area with a predetermined brightness is 1 to 200or above (i.e., the black area is at least 200 times larger than thewhite area). When the driver transistors 11 a of the pixels 16 areP-channel transistors, a voltage close to Vdd should be output, as aprecharge voltage, from the source driver circuit (IC) 14 (see FIG. 1).

However, as the precharge voltage PV gets closer to Vdd, a highervoltage resistance process is required for semiconductors used in thesource driver circuit (IC) 14 (the high voltage resistance, however, isonly on the order of 5 V to 10 V, but high voltage resistance in excessof 5 V increases the price of the semiconductor process). Thus, adoptionof a 5-volt resistance process makes it possible to use high-resolution,inexpensive processes.

If 5 V is not exceeded when the diode characteristics of the drivertransistors 11 a in pixels 16 are good and on-state current for whitedisplay is established, there is no problem because the 5-volt processcan also be used for the source driver IC 14. However, a problem ariseswhen the diode characteristics exceed 5 V. During precharging, inparticular, since a precharge voltage PV close to the source voltage Vddof the transistor 11 a must be applied, it is not possible to produceoutput from the IC 14.

FIG. 92 shows a panel configuration used to solve this problem. In FIG.92, a switch circuit 641 is formed on an array board 71. The sourcedriver IC 14 outputs an on/off signal for the switch 641. The on/offsignal is boosted by the level shifter circuit 693 formed on the arrayboard 71 and turns on and off the switch 641. Incidentally, the switch641 and level shifter circuit 693 are formed simultaneously orsequentially in a process of forming pixel transistors. Of course, anexternal circuit (IC) may be formed separately and mounted on the arrayboard 71.

The on/off signal is output from the terminal 761 a of the IC 14according to the precharge conditions described earlier (FIG. 75, etc.).Thus, needless to say, the precharge-voltage application and drivemethod are also applicable to the example shown in FIG. 92. The voltage(signal) outputted from the terminal 761 a is as low as 5 V or less. Thevoltage (signal) has its amplitude increased to the on/off logic levelof the switch 641 by the level shifter circuit 693.

With the above configuration, a power supply voltage capable of drivingthe programming current Iw in an operating voltage range is enough forthe source driver circuit (IC) 14. The precharge voltage PV poses noproblem for an array board 71 with a high operating voltage. Thus, theprecharge voltage can be applied sufficiently up to the level of theanode voltage (Vdd).

The switch 1521 in FIG. 89 also has a problem of voltage resistance ifformed (placed) in the source driver circuit (IC) 14. This is because,for example, if the voltage Vdd of the pixels 16 is higher than thepower supply voltage of the IC 14, there is a danger that a voltage highenough to break the IC 14 may be applied to the terminal 761 of the IC14.

An example which can solve this problem is shown in FIG. 91. A switchcircuit 641 is formed (placed) on an array board 71. Configuration andspecifications and the like of the switch circuit 641 are the same as orsimilar to those described with reference to FIG. 92.

The switch circuit 641 is placed ahead of the output of the IC 14 and inthe middle of the source signal line 18. As the switch 641 is turned on,the current Iw used to program the pixels 16 flows into the sourcedriver circuit (IC) 14. As the switch 641 is turned off, the sourcedriver circuit (IC) 14 is cut off from the source signal line 18. Bycontrolling the switch 641, it is possible to implement the drive systemand the like illustrated in FIG. 90.

The voltage (signal) outputted from the terminal 761 a is as low as 5 Vor less, as in the case of FIG. 92. The voltage (signal) has itsamplitude increased to the on/off logic level of the switch 641 by thelevel shifter circuit 693.

With the above configuration, a power supply voltage capable of drivingthe programming current Iw in an operating voltage range is enough forthe source driver circuit (IC) 14. Since the switch 641 also operates onthe power supply voltage of the array board 71, neither the switch 641nor the source driver circuit (IC) 14 is broken even if the voltage Vddis applied to the source signal line 18 from the pixels 16.

Incidentally, needless to say, both the switch 641 placed (formed) inthe middle of the source signal line 18 in the FIG. 91 and the switch641 for application of the precharge voltage PV may be formed (placed)on the array board 7l (examples include configurations shown in FIGS. 91and 92).

As described earlier, when the driver transistor 11 a and selectiontransistors (11 b and 11 c) of the pixel 16 are P-channel transistors asshown in FIG. 1, a penetration voltage is generated. This is becausepotential fluctuations of the gate signal line 17 a penetrates to aterminal of the capacitor 19 via G-S capacitance (parasitic capacitance)of the selection transistors (11 b and 11 c). When the P-channeltransistor 11 b turns off, the voltage is set to Vgh. As a result, theterminal voltage of the capacitor 19 shifts slightly to the Vdd side.Consequently, the gate (G) terminal voltage of the selection transistor11 a rises creating a more intense black display. This results in aproper black display.

However, although a completely black display can be achieved in the 0thgradation, it is difficult to display the 1st gradation and the like. Inother cases, a large gradation jump may occur between the 0th and 1stgradations or black reproduction may occur in a particular gradationrange. To solve this problem, a configuration in FIG. 71 is available.This configuration is characterized by comprising a function to padoutput current values. A main purpose of a padder circuit 711 is to makeup for the penetration voltage. It can also be used to adjust blacklevels so that some current (tens of nA) will flow even if image data isat black level 0.

Basically, FIG. 71 is the same as FIG. 64 except that the padder circuithas been added (enclosed by dotted lines in FIG. 71) to the outputstage. In FIG. 71, three bits (K0, K1, and K2) are used as currentpadding control signals. The three bits of control signals make itpossible to add a current value 0 to 7 times larger than the currentvalue of grandchild current sources to output current.

The above is a basic overview of the source driver circuit (IC) 14according to the present invention. Now, the source driver circuit (IC)14 according to the present invention will be described in more detail.

The current I (A) passed through the EL element 15 and emissionbrightness B (nt) have a linear relationship. That is, the current I (A)passed through the EL element 15 is proportional to the emissionbrightness B (nt). In current driving, each step (gradation step) isprovided by current (unit transistor 634 (single-unit)).

Human vision with respect to brightness has square-law characteristics.In other words, quadratic brightness changes are perceived to be linearbrightness changes. However, according to the relationship shown in FIG.83, the current I (A) passed through the EL element 15 is proportionalto the emission brightness B (nt) both in low brightness and highbrightness regions. Thus, if brightness is varied step by step (atintervals of one gradation), brightness changes greatly in each step(loss of shadow detail occurs) in a low gradation part (black area). Ina high gradation part (white area), since brightness changes coincideapproximately with a linear segment of a quadratic curve, the brightnessis perceived to change at equal intervals in each step. Thus, how todisplay a black display area, in particular, becomes a problem incurrent driving (in which each step is provided as an increment ofcurrent) (i.e., in a current-driven source driver circuit (IC) 14).

To solve this problem according to the present invention, the slope ofoutput current is decreased in the low gradation region (from gradation0 (complete black display) to gradation (R1)) and the slope of outputcurrent is increased in the high gradation region (from gradation R1 tothe highest gradation (R)) as illustrated in FIG. 79. That is, a currentincrement per gradation (in each step) is decreased in the low gradationregion and a current increment per gradation (in each step) is increasedin the high gradation region. By varying the amount of change in currentbetween the two gradation regions in FIG. 79, it is possible to bringgradation characteristics close to a quadratic curve, and thus eliminateloss of shadow detail in the low gradation region. Gradation-currentcharacteristics curves illustrated in FIG. 79 and the like are referredto as gamma curves.

Incidentally, although two current slopes—in the low gradation regionand high gradation region—are used in the above example, this is notrestrictive. Needless to say, three or more slopes may be used. Needlessto say, however, the use of two slopes is preferable because itsimplifies circuit configuration. Preferably, a gamma circuit is capableof generating five or more slopes.

A technical idea of the present invention lies in the use of two or morevalues of current increment per gradation step in a current-drivensource driver circuit (IC) and the like (basically, the circuit usescurrent outputs for gradation display. Thus, display panels are notlimited to the active-matrix type and include the simple-matrix type).

In EL and other current-driven display panels, display brightness isproportional to the amount of current applied. Thus, the source drivercircuit (IC) 14 according to the present invention can adjust thebrightness of the display panel easily by adjusting a reference currentwhich provides a basis for a current flowing through one current source(one unit transistor) 634.

In EL display panels, luminous efficiency varies among R, G, and B andcolor purity deviates from that of the NTSC standard. Thus, to obtain anoptimum white balance, it is necessary to optimize ratios among R, G,and B. The optimization is performed by adjusting the RGB referencecurrents separately. For example, the reference current for R is set to2 μA, the reference current for G is set to 1.5 μA, and the referencecurrent for B is set to 3.5 A. Preferably, at least one of the referencecurrents for different colors can be changed, adjusted, or controlled,as described above.

The source driver circuit (source driver IC) 14 according to the presentinvention decreases the current mirror factor of the first-stage currentsource 631 in FIGS. 67, 148, etc. (e.g., the current flowing through thetransistor 632 b is reduced to 1/100, i.e., to 10 nA if a referencecurrent is 1 μA) to make it possible to roughly adjust the referencecurrent from outside and accurately adjust minute current within thechip. Needless to say, the above items also apply to the referencecurrent Ib in FIG. 147 as well as to the reference currents Ib and Ic inFIGS. 157, 158, 159, 160, 161, 163, 164, 165, etc.

Adjustment circuits for reference currents in low gradation regions andadjustment circuits for reference currents in high gradation regions areprovided to achieve the gamma curve in FIG. 79. Incidentally, FIG. 79shows a gradation control method generated by a single-point polygonalgamma circuit. This is intended for ease of explanation and the presentinvention is not limited to this. Needless to say a multi-pointpolygonal gamma circuit may be used.

Also, although not shown, adjustment circuits for reference currents inlow gradation regions and adjustment circuits for reference currents inhigh gradation regions are provided separately for R, G, and B so thatadjustments can be made separately for R, G, and B. Of course,adjustment circuits for reference currents in low gradation regions andadjustment circuits for reference currents in high gradation regions maybe provided for only two colors if white balance is adjusted by fixingone color and adjusting the reference currents for two colors (i.e., Rand B if G is fixed).

In the case of current driving, the current I passed through the ELelement and brightness have a linear relationship as also illustrated inFIG. 83. To adjust white balance through a mixture of R, G, and B, itsuffices to adjust the reference currents for R, G, and B at only onepredetermined brightness. In other words, if the white balance isadjusted by adjusting the reference currents for R, G, and B at thepredetermined brightness, basically a white balance can be achieved overthe entire range of gradations. Thus, the present invention ischaracterized by comprising adjustment means of adjusting the referencecurrents for R, G, and B as well as a single-point polygonal ormulti-point polygonal gamma curve generator circuit (generating means).The above is a circuit arrangement peculiar to current-controlled ELdisplay panels rather than liquid crystal display panels circuit.

The gamma curve in FIG. 79 causes a problem when used for liquid crystaldisplay panels. To achieve an RGB white balance, the gamma curve musthave the same breakpoint location (gradation R1) for R, G, and B. Thecurrent driving according to the present invention can accommodate thisproblem because it can make relative positions in the gamma curve equalamong R, G, and B. Also, the ratio between slope in a low gradationregion and slope in a high gradation region must be the same among R, G,and B. The current driving according to the present invention canaccommodate this problem because it can make relative positions in thegamma curve equal among R, G, and B.

Thus, the current driving according to the present invention operates onthe principle that there is a linear relationship between the current Iapplied to the pixel 16 and emission brightness of the EL element 15 asillustrated in FIG. 83 although the slope differ among R, G, and B. Theuse of this relationship makes it possible to implement a gamma circuitsmall in scale without disturbing white balance in each gradation.

The gamma circuit of the present invention increments, for example, 10nA per gradation in a low gradation region (corresponding to the slopeof a gamma curve in the low gradation region). In a high gradationregion, it increments 50 nA per gradation (corresponding to the slope ofa gamma curve in the high gradation region).

Incidentally, the ratio of the current increment per gradation in thehigh gradation region to the current increment per gradation in the lowgradation region is referred to as a gamma current ratio. According tothis example, the gamma current ratio is 50 nA/10 nA=5. The same gammacurrent ratio should be used for R, G, and B. In other words, thecurrent (programming current) flowing through the EL elements 15 iscontrolled with the gamma current ratio kept the same for R, G, and B.

FIG. 80 shows an example of gamma curves. In FIG. 80(a), the currentincreases in large per-gradation increments both in the low and highgradation regions. In FIG. 80(b), the current increases in smallerper-gradation increments both in the low and high gradation regions thanin FIG. 80(a). However, both in FIG. 80(a) and FIG. 80(b), the gammacurrent ratio is the same for R, G, and B.

If current is adjusted with the gamma current ratio kept the same for R,G, and B in this way, it becomes easier to configure the circuit. Thenit suffices to build, for each of R, G, and B, a constant-currentcircuit which generates a reference current to be applied to the lowgradation part and constant-current circuit which generates a referencecurrent to be applied to the high gradation part and build (place) aregulator which relatively adjusts the current passed through theconstant-current circuits.

FIG. 77 shows a circuit configuration which varies output current whilemaintaining a gamma current ratio. A current control circuit 772 variesthe current passed through current sources 633L and 633H whilemaintaining the gamma current ratio between a reference current source771L for low current regions and reference current source 771H for highcurrent regions.

Preferably, temperature of the display panel is detected with atemperature detection circuit 781 formed in the IC chip (circuit) 14 asillustrated in FIG. 78. This is because organic EL elements for R, G,and B vary in temperature characteristics depending on their material.The temperature detection is performed using a bipolar transistor formedin the temperature detection circuit 781. This is based on the principlethat junctions of the bipolar transistor change their state withtemperature, causing output current of the bipolar transistor to varywith the temperature. The detected temperature is fed back to atemperature control circuit 782 placed (formed) for each color, to allowthe current control circuit 772 to make temperature compensation.

Incidentally, an appropriate gamma ratio is between 3 and 10 (bothinclusive). More preferably, the gamma ratio is between 4 and 8 (bothinclusive). Preferably, the gamma current ratio, in particular, isbetween 5 and 7 (both inclusive). The above relations will be referredto as a first relationship.

It is appropriate to set a transition point (gradation R1 in FIG. 79)between the low gradation part and high gradation part to between 1/32and ¼ of the maximum number K of gradations (both inclusive) (e.g., ifthe maximum number K of gradations is 64 gradations corresponding to6-bit data, the transition point should be set to between the 2ndgradation (=64/32) and 16th gradation (=64/4)). More preferably, thetransition point (gradation R1 in FIG. 79) between the low gradationpart and high gradation part is set to between 1/16 and ¼ of the maximumnumber K of gradations (both inclusive) (e.g., if the maximum number Kof gradations is 64 gradations corresponding to 6-bit data, thetransition point should be set to between the 4th gradation (=64/16) and16th gradation (=64/4)). Still more preferably, it is set to between1/10 and ⅕ of the maximum number K of gradations (both inclusive)(incidentally, any fractional part is rounded off. For example, if themaximum number K of gradations is 64 gradations corresponding to 6-bitdata, the transition point should be set to between the 6th gradation(=64/10) and 12th gradation (=64/5)). The above relations will bereferred to as a second relationship.

Incidentally, the above description concerns gamma current ratiosbetween two current regions. However, the second relationship alsoapplies to gamma current ratios among three or more current regions(i.e., where there are two or more breakpoints). That is, therelationship can be applied to any two of three or more slopes.

By satisfying the first and second relationships, it is possible toachieve proper image display free of loss of shadow detail.

FIG. 82 shows an example in which a plurality of the current-drivensource driver circuits (ICs) 14 according to the present invention areused for one display panel. The present invention assumes that aplurality of the source driver ICs 14 are used. The source driver ICs 14have a slave/master (S/M) terminal.

When the S/M terminal is set to high, the source driver circuit 14operates as a master chip and outputs a reference current through areference current output terminal (not shown) This current flows to theINL and INH terminals (in FIGS. 73 and 74) of slave ICs 14 (14 a and 14c). When the S/M terminal is set to low, the source driver circuit 14operates as a slave chip and receives a reference current from a masterchip through a reference current input terminal (not shown). Thiscurrent flows to the INL and INH terminals in FIGS. 73 and 74.

Different reference currents are passed between the reference currentinput terminal and reference current output terminal for differentcolors in the two gradation regions: low and high. In the case of RGBthree colors, this means 6 (=3×6) kinds of reference current.Incidentally, although two kinds of reference current are used for eachcolor in the above example, this is not restrictive and three or morekinds of reference current may be used for each color.

The current driving according to the present invention allows abreakpoint (gradation R1 and the like) to be changed as illustrated inFIG. 81. In FIG. 81(a), the low gradation part and high gradation partare divided by gradation R1 while in FIG. 81(b), the low gradation partand high gradation part are divided by gradation R2. In this way, thebreakpoint location may be selected from among a plurality of locations.

Specifically, the present invention can achieve a 64-gradation display.The breakpoint (gradation R1) can be set to any of the following: none,2nd gradation, 4th gradation, 8th gradation, and 16th gradation.Incidentally, the reason why the breakpoint can be the 2nd, 4th, 8th, or16th gradation is that completely black display corresponds to the 0thgradation. If completely black display corresponds to the 1st gradation,the breakpoint can be the 3rd, 5th, 9th, 17th, or 33rd gradation. Inthis way, if the breakpoint is set to the n-th gradation (or (n+1)-thgradation if completely black display corresponds to the 1st gradation)where n is a power of two, circuit configuration is made easier.

FIG. 73 is a block diagram showing a current source circuit portion fora low-current region. FIG. 74 is a block diagram showing a currentsource portion for a high-current region and padder current circuitportion. As shown in FIG. 73, a reference current INL is applied to thelow-current source circuit portion. Basically, this current serves as aunit current, a required number of unit transistors 634 operateaccording to input data L0 to L4, and the total current flows as aprogramming current IwL for the low-current portion.

Also, as shown in FIG. 74, a reference current INH is applied to thehigh-current source circuit portion. Basically, this current serves as aunit current, a required number of unit transistors 634 operateaccording to input data H0 to L5, and the total current flows as aprogramming current IwH for the low-current portion.

The same applies to the padder current circuit portion. As shown in FIG.74, a reference current INH is applied to it. Basically, this currentserves as a unit current, a required number of unit transistors 634operate according to input data AK0 to AK2, and the total current flowsas a current IwK which corresponds to a padding current.

The programming current Iw flowing to the source signal line 18 is givenby Iw=IwH+IwL+IwK.

The ratio of IwH to IwL, i.e., the gamma current ratio should satisfythe first relationship described earlier.

As illustrated in FIGS. 73 and 74, the on/off switch 641 consists of aninverter 732 and an analog switch 731 which in turn consists of aP-channel transistor and N-channel transistor. This configuration canreduce on-resistance and minimize voltage drops between the unittransistor 634 and the source signal line 18. Needless to say, this alsoapplies to other examples of the present invention.

Now, description will be given of the low-current circuit portion inFIG. 73 and high-current circuit portion in FIG. 74. The source drivercircuit (IC) 14 according to the present invention consists of 5 bits(L0 to L4) in the low-current circuit portion and 6 bits (H0 to H5) inthe high-current circuit portion. Incidentally, the data fed into thecircuits from outside consists of 6 bits D0 to D5 (64 gradations foreach color). The 6-bit data is converted into 5-bit data (L0 to L4) and6-bit data (H0 to H5) in the high-current circuit portion, and then theprogramming current Iw corresponding to image data is applied to thesource signal line. That is, the 6-bit input data is converted into11-bit data (=5+6). This makes it possible to form a high-accuracy gammacurve.

As described above, the 6-bit input data is converted into 11-bit data(=5+6). According to the present invention, the bit count (H) in thehigh-current region of the circuit is equal to the bit count of inputdata (D) while the bit count (L) in the low-current region of thecircuit is equal to the bit count of input data (D) minus 1.Incidentally, the bit count (L) in the low-current region of the circuitmay be the bit count of input data (D) minus 2. This configurationoptimizes the gamma curve in the low-current region and gamma curve inthe high-current region for image display on the EL display panel.

A control method for circuit control data (L0 to L4) in the low-currentregion and circuit control data (H0 to H4) in the high-current regionwill be described below with reference to FIGS. 84 and 86.

The present invention is characterized by operation of the unittransistor 634 a connected to an L4 terminal in FIG. 73. The unittransistor 634 a consists of a transistor which serves as a single-unitcurrent source. By turning on and off this transistor, the programmingcurrent Iw can be controlled easily (on/off control).

FIG. 84 shows signals applied to low-current signal lines (L) andhigh-current signal lines (H) when the low-current region andhigh-current region are divided by the 4th gradation. Incidentally,although the 0th to 18th gradations are shown in FIGS. 84 to 86,actually there are gradations up to the 63rd gradation. In this way, thegradations higher than the 18th gradation are omitted in every drawing.The switch 641 turns on when the appropriate value in the table is “1”to connect the appropriate unit transistor 634 with the source signalline 18 and the switch 641 turns off when the appropriate value in thetable is “0.”

Referring to FIG. 84, in the 0th gradation which corresponds tocompletely black display, (L0 to L4)=(0, 0, 0, 0, 0) and (H0 to H5)=(0,0, 0, 0, 0). Thus, all the switches 641 are off and the programmingcurrent Iw applied to the source signal line 18 is 0.

In the 1st gradation, (L0 to L4)=(1, 0, 0, 0, 0) and (H0 to H5)=(0, 0,0, 0, 0). Thus, one unit transistor 634 in the low-current region isconnected to the source signal line 18. No unit current source in thehigh-current region is connected to the source signal line 18.

In the 2nd gradation, (L0 to L4)=(0, 1, 0, 0, 0) and (H0 to H5)=(0, 0,0, 0, 0). Thus, two unit transistors 634 in the low-current region areconnected to the source signal line 18. No unit current source in thehigh-current region is connected to the source signal line 18.

In the 3rd gradation, (L0 to L4)=(1, 1, 0, 0, 0) and (H0 to H5)=(0, 0,0, 0, 0). Thus, two switches 641La and 641Lb in the low-current regionturn on and three unit transistors 634 are connected to the sourcesignal line 18. No unit current source in the high-current region isconnected to the source signal line 18.

In the 4th gradation, (L0 to L4)=(1, 1, 0, 0, 1) and (H0 to H5)=(0, 0,0, 0, 0). Thus, three switches 641La, 641Lb, and 641Le in thelow-current region turn on and four unit transistors 634 are connectedto the source signal line 18. No unit current source in the high-currentregion is connected to the source signal line 18.

In the 5th and higher gradations, there is no change in the low-currentregion, i.e., (L0 to L4)=(1, 1, 0, 0, 1). In the high-current region,however, (H0 to H5)=(1, 0, 0, 0, 0) in the 5th gradation. Thus, a switch641Ha turns on and one unit current source 641 in the high-currentregion is connected to the source signal line 18. In the 6th gradation,(H0 to H5)=(0, 1, 0, 0, 0). Thus, a switch 641Hb turns on and two unitcurrent sources 641 in the high-current region are connected to thesource signal line 18. Similarly, in the 7th gradation, (H0 to H5)=(1,1, 0, 0, 0). Thus, two switches 641Ha and 641Hb turn on and three unitcurrent sources 641 in the high-current region are connected to thesource signal line 18. In the 8th gradation, (H0 to H5)=(0, 0, 1, 0, 0).Thus, a switch 641Hc turns on and four unit current sources 641 in thehigh-current region are connected to the source signal line 18 asillustrated in FIG. 84. Subsequently, switches 641 turn on and off insequence and the programming current Iw is applied to the source signalline 18.

A feature of the above operations is that after the breakpoint, theprogramming current Iw applied to the high gradation part is composed ofthe current for the low gradation part plus a current which correspondsto each step (gradation) in the high gradation part. A change point ofthe low-current region and the high-current region, specifically, in thehigh-current region, for the programming current Iw, low current IwL isadded. Therefore, the reference to “change point” may not be correct. Apadding current IwK is also added.

Also, control bits (L) in the low gradation region do not change after agradation step (a point or location where current changes, to be exact).At this time, the L4 terminal in FIG. 73 is set to “1,” the switch 641 eturns on, and current flows through the unit transistor 634 a.

Thus, in the 4th gradation in FIG. 84, four unit transistors (currentsources) 634 in the low gradation part are in operation. In the 5thgradation, four unit transistors (current sources) 634 in the lowgradation part are in operation and one transistor (current sources) 634in the high gradation part is in operation. Similarly, in the 6thgradation, four unit transistors (current sources) 634 in the lowgradation part are in operation and two transistors (current sources)634 in the high gradation part are in operation. Thus, in the 5thgradation which corresponds to a breakpoint and in the subsequentgradations, as many current sources 634 as there are gradations (four inthis case) in the low gradation region below the breakpoint remain onand current sources 634 in the high gradation region turn on in sequencecorresponding to the gradation.

It can be seen that the unit transistor 634 a at the terminal L4 in FIG.73 operates effectively. Without this transistor 634 a, a unittransistor 634 in the high gradation part would turn on after the 3rdgradation. Thus, the change point does not fall on a power of 2 such as4, 8, or 16. A power of 2 results when only one signal goes “1.”

This makes it easy to judge whether a weighting signal line by 2 is setto “1.” Consequently, the hardware scale required for the judgment canbe reduced. In other words, IC chip logic circuits can be simplified,making it possible to design an IC with a small chip area (resulting inlow costs).

FIG. 85 is an explanatory diagram illustrating signals applied tolow-current signal lines (L) and high-current signal lines (H) when thelow-current region and high-current region are divided by the 8thgradation.

Referring to FIG. 85, in the 0th gradation which corresponds tocompletely black display, (L0 to L4)=(0, 0, 0, 0, 0) and (H0 to H5)=(0,0, 0, 0, 0), as in the case of FIG. 84. Thus, all the switches 641 areoff and the programming current Iw applied to the source signal line 18is 0.

Similarly, in the 1st gradation, (L0 to L4)=(1, 0, 0, 0, 0) and (H0 toH5)=(0, 0, 0, 0, 0). Thus, one unit transistor 634 in the low-currentregion is connected to the source signal line 18. No unit current sourcein the high-current region is connected to the source signal line 18.

In the 2nd gradation, (L0 to L4)=(0, 1, 0, 0, 0) and (H0 to H5)=(0, 0,0, 0, 0). Thus, two unit transistors 634 in the low-current region areconnected to the source signal line 18. No unit current source in thehigh-current region is connected to the source signal line 18.

In the 3rd gradation, (L0 to L4)=(1, 1, 0, 0, 0) and (H0 to H5)=(0, 0,0, 0, 0). Thus, two switches 641La and 641Lb in the low-current regionturn on and three unit transistors 634 are connected to the sourcesignal line 18. No unit current source in the high-current region isconnected to the source signal line 18.

Similarly, in the 4th gradation, (L0 to L4)=(0, 0, 1, 0, 0) and (H0 toH5)=(0, 0, 0, 0, 0). In the 5th gradation, (L0 to L4)=(1, 0, 1, 0, 0)and (H0 to H5)=(0, 0, 0, 0, 0). In the 6th gradation, (L0 to L4)=(0, 1,1, 0, 0) and (H0 to H5)=(0, 0, 0, 0, 0). In the 7th gradation, (L0 toL4)=(1, 1, 1, 0, 0) and (H0 to H5)=(0, 0, 0, 0, 0).

The 8th gradation corresponds to a change point (breakpoint location).In the 8th gradation, (L0 to L4)=(1, 1, 1, 0, 1) and (H0 to H5)=(0, 0,0, 0, 0). Thus, four switches 641La, 641Lb, 641Lc, and 641Le in thelow-current region turn on and eight unit transistors 634 are connectedto the source signal line 18. No unit current source in the high-currentregion is connected to the source signal line 18.

In the 8th and higher gradations, there is no change in the low-currentregion, i.e., (L0 to L4)=(1, 1, 1, 0, 1). In the high-current region,however, (H0 to H5)=(1, 0, 0, 0, 0) in the 9th gradation. Thus, theswitch 641Ha turns on and one unit current source 641 in thehigh-current region is connected to the source signal line 18.

Similarly, the number of unit transistors 634 in the high-current regionincreases one by one with increasing gradation steps. Specifically, inthe 10th gradation, (H0 to H5)=(0, 1, 0, 0, 0). The switch 641Hb turnson and two unit current sources 641 in the high-current region areconnected to the source signal line 18. Similarly, in the 11thgradation, (H0 to H5)=(1, 1, 0, 0, 0). Two switches 641Ha and 641Hb turnon and three unit current sources 641 in the high-current region areconnected to the source signal line 18. In the 12th gradation, (H0 toH5)=(0, 0, 1, 0, 0). The switch 641Hc turns on and four unit currentsources 641 in the high-current region are connected to the sourcesignal line 18. Subsequently, switches 641 turn on and off in sequenceand the programming current Iw is applied to the source signal line 18as illustrated in FIG. 84.

FIG. 86 is an explanatory diagram illustrating signals applied tolow-current signal lines (L) and high-current signal lines (H) when thelow-current region and high-current region are divided by the 16thgradation. Basic operation is the same as those in FIGS. 84 and 85.

Specifically, referring to FIG. 86, in the 0th gradation whichcorresponds to completely black display, (L0 to L4)=(0, 0, 0, 0, 0) and(H0 to H5)=(0, 0, 0, 0, 0), as in the case of FIG. 85. Thus, all theswitches 641 are off and the programming current Iw applied to thesource signal line 18 is 0. Similarly, from the first to the 16thgradations, (H0 to H5)=(0, 0, 0, 0, 0) in the high-current region. Thus,one unit transistor 634 in the low-current region is connected to thesource signal line 18. No unit current source in the high-current regionis connected to the source signal line 18. That is, only L0 to L4 in thelow-current region change.

Specifically, (L0 to L4)=(1, 0, 0, 0, 0) in the 1st gradation, (L0 toL4)=(0, 1, 0, 0, 0) in the 2nd gradation, (L0 to L4)=(1, 1, 0, 0, 0) inthe 3rd gradation, and (L0 to L4)=(0, 0, 1, 0, 0) in the 2nd gradation.This continues to the 16th gradation. Specifically, (L0 to L4)=(1, 1, 1,1, 0) in the 15th gradation and (L0 to L4)=(1, 1, 1, 1, 1) in the 16thgradation. In the 16th gradation, only the 5th bit (D4) out of D0 to D5which represent gradations turns on, and thus it can be determined fromthe data signal line (D4) that the data D0 to D5 represent the 16thgradation. This reduces the hardware scale required for logic circuits.

The 16th gradation corresponds to a change point (breakpoint location).Rather, it ought to be said that the 17th gradation corresponds to achange point. In the 16th gradation, (L0 to L4)=(1, 1, 1, 1, 1) and (H0to H5)=(0, 0, 0, 0, 0). Thus, four switches 641La, 641Lb, 641Lc, 641 d,and 641Le in the low-current region turn on and 16 unit transistors 634are connected to the source signal line 18. No unit current source inthe high-current region is connected to the source signal line 18.

In the 16th and higher gradations, there is no change in the low-currentregion, i.e., (L0 to L4)=(1, 1, 1, 0, 1). In the high-current region,however, (H0 to H5)=(1, 0, 0, 0, 0) in the 17th gradation. Thus, theswitch 641Ha turns on and one unit current source 641 in thehigh-current region is connected to the source signal line 18.

Similarly, the number of unit transistors 634 in the high-current regionincreases one by one with increasing gradation steps. Specifically, inthe 18th gradation, (H0 to H5)=(0, 1, 0, 0, 0). The switch 641Hb turnson and two unit current sources 641 in the high-current region areconnected to the source signal line 18. Similarly, in the 19thgradation, (H0 to H5)=(1, 1, 0, 0, 0). Two switches 641Ha and 641Hb turnon and three unit current sources 641 in the high-current region areconnected to the source signal line 18. In the 20th gradation, (H0 toH5)=(0, 0, 1, 0, 0). The switch 641Hc turns on and four unit currentsources 641 in the high-current region are connected to the sourcesignal line 18.

The above method results in extremely easy logic processing such asturning on (or turning off in an alternative configuration) currentsources (single-unit transistors) 634 equal in number to a power of twoor connecting them to the source signal line 18 at the change point(breakpoint location).

For example, if the breakpoint location corresponds to the 4th gradation(4 is a power of two) as illustrated in FIG. 84, four current sources(single unit) 634 turn on at this location. Then, current sources(single unit) 634 in the high-current region are added in the subsequentgradations.

On the other hand, if the breakpoint location corresponds to the 8thgradation (8 is a power of two) as illustrated in FIG. 85, eight currentsources (single unit) 634 turn on at this location. Then, currentsources (single unit) 634 in the high-current region are added in thesubsequent gradations. The present invention makes it possible toimplement a gamma control circuit with a small hardware configurationnot only for 64-gradation representation, but also for any gradationrepresentation (including 16-gradation representation with 4,096 colorsand 256-gradation representation with 16,700,000 colors).

Incidentally, although in the examples described with reference to FIGS.84, 85, and 86, it has been stated that the change point is set to then-th gradation where n is a power of two, this is true only whencompletely black display corresponds to the 0th gradation. If completelyblack display corresponds to the 1st gradation, 1 should be added to n.

What is important in the present invention is to provide a plurality ofcurrent regions (low-current region, high-current region, etc.) and beable to judge (process) a change point between the current regions usinga small number of signal inputs. For example, one technical idea behindthe present invention is that if a power of two is used, only a singlesignal line needs to be detected, reducing the hardware scale greatly.Also, a current source 634 a is added to ease the processing requiredfor that.

In the case of negative logic, the change point can be set to 1, 3, 7,15, or the like instead of 2, 4, 8, or the like. Also, although it hasbeen stated that the 0th gradation corresponds to completely blackdisplay, this is not restrictive. For example, in the case of64-gradation display, the 63rd gradation may be designated as completelyblack display and the 0th gradation may be designated as a maximum whitedisplay. In that case, the change point can be processed, taking intoconsideration the reverse direction. Thus, processing may not be basedon powers of two.

The change point (breakpoint location) is not limited to a single gammacurve. The circuits according to the present invention allows existenceof two or more breakpoint locations. For example, breakpoint locationsmay be set to the 4th and 16th gradations. Alternatively, breakpointlocations may be set to more than two locations such as the 4th, 16th,and 32nd gradations.

In the above example, the breakpoint is set to the n-th gradation wheren is a power of two, but this is not restrictive. For example, abreakpoint may be set to the gradation given by the sum of 2 and 8 whichare powers of two (2+8=10; i.e., two signal lines are needed forjudgment). Alternatively, a breakpoint may be set to the gradation givenby the sum of 2, 8, and 16 which are powers of two (2+8+16=28; i.e.,three signal lines are needed for judgment). In that case, the hardwarescale required for judgment or processing is increased more or less, butis not difficult to deal with in terms of circuit configuration. Also,needless to say, the above items are included in the technical scope ofthe present invention.

As illustrated in FIG. 87, the source driver circuit (IC) 14 accordingto the present invention consists of three current output circuits 704.They are a high-current-region current output circuit 704 a whichoperates in a high current region, low-current-region current outputcircuit 704 b which operates in low and high current regions, and alow-current-region current output circuit 704 b which outputs a paddingcurrent.

The high-current-region current output circuit 704 a and thecurrent-padding current output circuit 704 c operate with a referencecurrent source 771 a which outputs high current, as reference current,while the low-current-region current output circuit 704 b operates witha reference current source 771 b which outputs low current, as referencecurrent.

As also described earlier, the number of current output circuits 704 isnot limited to three: the high-current-region current output circuit 704a, low-current-region current output circuit 704 b, and current-paddingcurrent output circuit 704 c. The source driver circuit (IC) 14 mayconsists of two current output circuits 704—the high-current-regioncurrent output circuit 704 a and low-current-region current outputcircuit 704 b—or three or more current output circuits 704. Also,reference current sources 771 may be placed or formed for respectivecurrent output circuits 704 or a common reference current source 771 maybe provided for all the current output circuits 704.

The current output circuits 704 respond to gradation data, and unittransistors 634 in them operate by drawing current from the sourcesignal line 18. Said and unit transistors 634 operate in sync with ahorizontal scanning period (1 H) signal. That is, current is fed basedon appropriate gradation data for a period of 1 H (if the unittransistors 634 are N-channel transistors).

On the other hand, the gate driver circuit 12 selects gate signal lines17 a basically one by one in sync with the 1 H signal. That is, in syncwith the 1-H signal, the gate signal line 17 a(1) is selected in thefirst horizontal scanning period, gate signal line 17 a(2) is selectedin the second horizontal scanning period, gate signal line 17 a(3) isselected in the third horizontal scanning period, and gate signal line17 a(4) is selected in the fourth horizontal scanning period.

However, between the time when the first gate signal line 17 a isselected and the time when the second gate signal line 17 a is selected,there is a period in which no gate signal line 17 a is selected(non-selection period; see t1 in FIG. 88). A rise period and fall periodof the first gate signal line 17 a are needed for non-selected period inorder to secure an on/off control period for the selection transistor 11d.

If a turn-on voltage is applied to any of the gate signal lines 17 a andthe transistor 11 b and selection transistor 11 c of the pixel 16 areon, programming current Iw flows from the Vdd power supply (anodevoltage) to the source signal line 18 via the driver transistor 11 a.The programming current Iw flows through the unit transistors 634 (for aperiod of t2 in FIG. 88). Incidentally, parasitic capacitance C ispresent in the source signal line 18 (the parasitic capacitance iscaused by capacitance at junctions of the source signal line and gatesignal lines).

However, when no gate signal line 17 a is selected (non-selectionperiod; t1 in FIG. 88), there is no current path on the transistor 11 a.Since the unit transistors 634 pass current, electric charges areabsorbed from parasitic capacitance on the source signal line 18. Thislowers the potential of the source signal line 18 (part A in FIG. 88).As the potential of the source signal line 18 lowers, it takes time towrite current for the next image data.

To solve this problem, a switch 641 a is formed at an output end of thesource terminal 761 as illustrated in FIG. 89. Also, a switch 641 b isformed or placed in the output stage of the current-padding currentoutput circuit 704 c.

During the non-selection period t1, a control signal is applied to acontrol terminal S1 and the switch 641 a is turned off. During theselection period t2, the switch 641 a is turned on (conducting). Theprogramming current Iw=IwH+IwL+IwK flows when the switch 641 a is on.When the switch 641 a is turned off, the current Iw does not flow. Thus,as illustrated in FIG. 90, the potential falls to the level indicated byA in FIG. 88 (no change). Incidentally, the channel width W of theanalog switch 731 in the switch 641 should be between 10 and 100 μm(both inclusive). The channel width W of the analog switch must be 10 μmor larger to reduce on-resistance. However, it must be no larger than100 μm because too large W will increase parasitic capacitance. Morepreferably, the channel width W is between 15 and 60 μm (bothinclusive).

The switch 641 b performs control only during low gradation display.During low gradation display (black display), the gate potential of thepixel 16 transistor 11 a must be close to Vdd (thus, during blackdisplay, the potential of the source signal line 18 must be close toVdd). Also, during black display, the programming current Iw is small,and once the potential falls as indicated by A in FIG. 88, it takes timefor the potential to return to normal.

Thus, during low gradation display, non-selection periods t1 must beavoided. In contrast, during high gradation display, since theprogramming current Iw is large, non-selection periods t1 often do notpresent a problem. Thus, according to the present invention, when imagesare written for high gradation display, both switch 641 a and switch 641b are kept on even during non-selection periods. Also, the paddingcurrent IwK must be shut off to achieve black display to the utmost.When images are written for low gradation display, the switch 641 a iskept on and the switch 641 b is kept off even during non-selectionperiods. The switch 641 b is controlled via terminal S2.

Incidentally, it is also possible to keep the switch 641 a off(non-conducting) and keep the switch 641 b on (conducting) for both lowgradation display and high gradation display during non-selectionperiods t1. Off course, both switches 641 a and 641 b may be kept off(non-conducting) for both low gradation display and high gradationdisplay during non-selection periods t1. In either case, the switches641 can be controlled by controlling the control terminals S1 and S2.Incidentally, the control terminals S1 and S2 are controlled via commandcontrol.

For example, the control terminal S2 sets a t3 period to logic 0 in sucha way as to overlap the non-selection period t1. This control eliminatesthe condition indicated by A in FIG. 88. When the gradation representsblack display deeper than a certain level, the control terminal S1 isset to logic 0. Then, the padding current IwK is stopped to create amore intense black display.

In a typical driver IC, protective diodes 1671 are formed near theoutput (see FIG. 167). The protective diodes 1671 are formed to preventthe IC 14 from being broken by static electricity from outside.Generally, the protective diodes 1671 are formed between the outputwiring 643 and power supply Vcc or between the output wiring 643 andground.

The protective diodes 1671 are effective for prevention fromelectrostatic damage. However, static electricity is regarded as acapacitor (parasitic capacitance) in an equivalent circuit diagram. Incurrent driving, presence of parasitic capacitance at an output terminal643 makes current writing difficult.

The present invention provides a method of solving this problem. Thesource driver IC 14 is manufactured with the protective diodes 1671formed in the output stage. The manufactured source driver IC 14 ismounted or placed on an array board 71 and the output terminals 761 areconnected to the source signal lines 18. After the output terminals 761are connected to the source signal lines 18, the output wiring 643 iscut at points a and b with laser light 1502 as illustrated in FIG.169(a) to cut off the protective diodes 1671. Also, as illustrated inFIG. 169(b), laser light 1502 is directed at points c and d to cut thewiring. Thus, the protective diodes 1671 become isolated.

In this way, by cutting off the protective diodes 1671 from the outputwiring 643 or isolating the protective diodes 1671, it is possible toprevent the protective diodes 1671 from producing parasitic capacitance.Also, since the protective diodes 1671 are cut off from the outputwiring 643 or isolated after the IC 14 is mounted, there is no problemof electrostatic damage.

Incidentally, the laser light 1502 is directed at the back surface ofthe array board 71 as illustrated in FIG. 168. The array board 71, whichis made of glass, has optical transparency. Thus, the laser light 1502can pass through the array board 71.

It has been assumed in the above example that one source driver IC 14 ismounted on the display panel. However, the present invention is notlimited to this arrangement. A plurality of source driver ICs 14 may bemounted on the display panel. For example, FIG. 93 shows an example inwhich three source driver ICs 14 are mounted on a display panel.

As also described with reference to FIG. 82, the source driver IC 14according to the present invention supports the use of two or morecurrent-driven source driver circuits (ICs) 14. Thus, the source driverIC 14 has a slave/master (S/M) terminal. When the S/M terminal is set tohigh, the source driver circuit 14 operates as a master chip and outputsa reference current through a reference current output terminal (notshown). Of course the logic of the S/M terminal may be reversed.

Slave/master switching may be done through commands given to the sourcedriver IC 14. The reference current is transmitted via a cascade currentconnection line 931. When the S/M terminal is set to low, the IC 14operates as a slave chip and receives a reference current from a masterchip through a reference current input terminal (not shown). Thiscurrent flows to the INL and INH terminals in FIGS. 73 and 74.

To take an example, the reference current is generated by the currentoutput circuit 704 right at the center of the IC chip 14. The referencecurrent for the master chip is adjusted with an external resistor or aninternal step-current electronic regulator before it is applied.

A control circuit (command decoder) and the like are also formed(placed) in the center of the IC chip 14. The reason why the referencecurrent source is formed in the center of the chip is to minimize thedistance to the reference current generator circuits and programmingcurrent output terminals 761.

In the configuration in FIG. 93, reference current is transmitted from amaster chip 14 b to two slave chips (14 a and 14 c). Upon receiving thereference current, the slave chips generate parent, child, andgrandchild currents based on the received reference current.Incidentally, the master chip 14 b delivers current to the slave chipsas current-based delivery between current mirror circuits (see FIG. 67).The use of current-based delivery eliminates deviations in referencecurrent among the chips as well as parting lines on the screen.

FIG. 94 conceptually illustrates locations of terminals among whichreference current is delivered. In the center of the IC chip, referencecurrent signal lines 932 are connected to signal input terminals 941 i.

The current (or voltage; see FIG. 76) applied to the reference currentsignal lines 932 has been compensated for the temperaturecharacteristics of the EL material. Also, it has been compensated foraging of the EL material.

Based on the current (voltage) applied to the reference current signallines 932, current sources (631, 632, 633, and 634) are driven in thechip 14. The reference currents produced here are output as referencecurrents for the slave chips via current mirror circuits. The referencecurrents for the slave chips are output from terminals 941 o. At leastone terminal 941 o is placed (formed) on each side of the current outputcircuit 704. In FIG. 94 two terminals 9410 are placed (formed) on eachside. The reference currents are transmitted to the slave chips 14 viacascade signal lines 931 a 1, 931 a 2, 931 b 1, and 931 b 2.Incidentally, it is also possible to adopt a circuit configuration inwhich the reference current applied to the slave chip 14 a is fed backto the master chip 14 b to correct deviations. Problems encountered inmodularizing an organic EL display panel includes resistance values ofanode wiring 951 and cathode wiring.

In the organic EL display panel, although EL elements 15 require arelatively low drive voltage, a large current flows through the ELelements 15. Thus, it is necessary to increase the size of the anodewiring and cathode wiring which supply current to EL element 15. Forexample, even in a 2-inch class EL display panel, if polymeric ELmaterial is used, 200-mA or higher current must be passed through theanode wiring 951. To reduce voltage drops in the anode wiring 951, theresistance of the anode wiring 951 must be reduced to 1 Ω or below.However, with an array board 71, on which wiring is formed by thin filmvapor deposition, it is difficult to reduce resistance. Therefore, it isnecessary to increase pattern width. However, to transmit a 200-mAcurrent with minimum voltage drop, the wiring must be at least 2 mmwide.

FIG. 105 shows a configuration of a conventional EL display panel.

Built-in gate driver circuits 12 a and 12 b are formed (placed) on bothsides of a display screen 50. A source driver circuit 14 p (built-insource driver circuit) is formed through the same process as pixel 16transistors.

Anode wiring 951 is placed on the right of the panel. A Vdd voltage isapplied to the anode wiring 951. The width of the anode wiring 951 is 2mm or more, for example. The anode wiring 951 running along the bottomof the screen branches to the top of the screen. The number of branchesis equal to the number of pixel columns. For example, a QCIF panel has528 (=176×RGB) pixel columns. On the other hand, source signal lines 18come out of the built-in source driver circuit 14p. The source signallines 18 are run (formed) from top to bottom of the screen. Power supplywirings 1051 of the built-in gate driver circuits 12 are also placed onthe left and right of the screen.

Thus, bezel width on the right side of the display panel cannot bereduced. Today, reduction of bezel width is important for display panelsused for cell phones and the like. It is also important to provide equalbezel width on the left and right of the screen. With the configurationin FIG. 105, however, it is difficult to reduce bezel width.

To solve this problem, in the display panel according to the presentinvention, the anode wiring 951 is placed (formed) on the surface of thearray behind the source driver IC 14 as illustrated in FIG. 106. Thesource driver circuit (IC) 14 is made of a semiconductor chip andmounted on the array board 71 using COG (chip-on-glass) technology. Theanode wiring 951 can be placed (formed) on the source driver IC 14because under the chip 14 is a 10-μm to 30-μm space perpendicular to theboard.

As shown in FIG. 105, if the source driver circuit 14 p is formeddirectly on the array board 71, it is difficult to form anode wiring(base anode line, anode voltage line, and trunk anode line) 951 above orbelow the source driver circuit 14 p due to issues of the number ofmasks, yields and noise.

Also, as illustrated in FIG. 106, a common anode line 962 is formed andthe base anode line 951 and common anode line 962 are short-circuited byconnection anode lines 961. One of the points is that the connectionanode lines 961 are formed in the center of the IC chip. The connectionanode lines 961 eliminates potential difference between the base anodeline 951 and common anode line 962. Another point is that anode wires952 branch off from the common anode line 962. This configurationeliminates routing of anode wiring 951 such as the one shown in FIG.105, and thus can achieve reduction of bezel width.

If the common anode line 962 is 20 mm long, if wiring width is 150 μm,and if sheet resistance of the wiring is 0.05 Ω/□, the value ofresistance is given by 20000 (μm)/150 (μm)×0.05 Ω=approx. 7 Ω. If bothends of the common anode line 962 are connected to the base anode line951 by a connection anode line 961 c, the common anode line 962 issupplied with power from both sides, and consequently an apparentresistance value is 3.5 Ω (=7 Ω/2). If this value is converted into aconcentrated distribution multiplier, the apparent resistance value ofthe common anode line 962 is further halved and becomes 2 Ω or less.Even if anode current is 100 mA, a voltage drop in the common anode line962 is 0.2 V or less. Furthermore, if the common anode line 962 and baseanode line 951 are short-circuited by the connection anode line 961 b inthe center, there is almost no voltage drop.

The present invention is characterized in that the base anode line 951is formed under the IC 14, that the common anode line 962 is formed,that the common anode line 962 is electrically connected to the baseanode line 951 (the connection anode line 961), and that the anode wires952 branch off from the common anode line 962.

Incidentally, the pixel configuration according to the present inventionis described by taking the pixel configuration in FIG. 1 as an example.Therefore, the cathode electrode is described as a solid electrode(electrode common to pixels 16) and the anode is described as beingwired. However, depending on the configuration of the driver transistor11 a (N-channel or P-channel) or on pixel configuration, it will benecessary to use a solid electrode as the anode and lay a wire as thecathode. Therefore, the present invention is not limited to laying anodewires. The present invention concerns an anode or cathode which needs tobe wired. Thus, if the cathode needs to be laid as a wire, descriptionof the anode herein can be applied to the cathode.

To reduce the resistance of anode wires (the base anode line 951, commonanode line 962, connection anode lines 961, anode wires 952), a thickfilm may be formed by laminating conductive material using anelectroless plating, electrolytic plating, or other technique afterlaying thin-film wiring or before patterning. The use of a thick filmincreases the cross-sectional area of wiring, and thereby reducesresistance. The above items similarly apply to the cathode. They alsoapply to the gate signal lines 17 and source signal lines 18.

The provision and use of common anode line 962 which is supplied withpower from both sides via the connection anode lines 961 is effectiveand the formation of the connection anode line 961 b (961 c) in thecenter enhances this effect. Also, the base anode line 951, common anodeline 962, and connection anode lines 961 form a loop, which can reduceelectric fields produced in the IC 14.

Preferably, the common anode line 962 and base anode line 951 are madeof the same metal material and the connection anode lines 961 are alsomade of the same metal material. Also, these anode lines are implementedusing a metal material or construction which forms an array and has avery low resistance value. Generally, they are implemented using thesame metal material and construction (SD layer) as the source signallines 18. The same material cannot be used for the spot where the commonanode line 962 and source signal line 18 intersect. Thus, another metalmaterial (the same material and construction as the gate signal lines17; GE layer) is used at the intersections, which are then electricallyinsulated with an insulating film. Of course, the anode lines may beconstructed by laminating a thin film made of the same material as thesource signal lines 18 and a thin film made of the same material as thegate signal lines 17.

Incidentally, although it has been stated that wiring such as a nodewiring (cathode wiring) is laid on the back surface of the source driverIC 14 to supply current to EL elements 15, this is not restrictive. Forexample, the gate driver circuits 12 may be constructed with an IC chipand this IC may be mounted by COG. Then, anode wiring and cathode wiringare laid (formed) on the back surface of the gate driver IC 12.

Thus, the present invention involves fabricating a driver IC with asemiconductor chip, mounting the IC directly on a substrate such as anarray board 71, and forming (fabricating) a power supply or groundpattern such as anode wiring and cathode wiring in a space on the backof the IC chip for an EL display apparatus or the like.

The above items will be described in more detail with reference to otherdrawings. FIG. 95 is an explanatory diagram illustrating part of adisplay panel according to the present invention. In FIG. 95, dottedlines indicate a position where the IC chip 14 will be placed. That is,the base anode line (anode voltage line, i.e., the anode wiring beforebranching) is formed (placed) on the back surface of the IC chip 14 andfront surface of the array board 71. In this example of the presentinvention, although it is stated that the anode wiring 951 beforebranching is formed on the back surface of the IC chips (12 and 14),this is only for ease of explanation. For example, cathode wiring orcathode film before branching may be formed (placed) instead of theanode wiring 951 before branching. Besides, power supply wirings 1051 ofthe gate driver circuits 12 may be placed or formed.

The IC chip 14 has its current output (current input) terminals 741connected by COG technology with connection terminals 953 formed on thearray board 71. The connection terminal 953 is formed on one end of eachsource signal line 18. The connection terminals 953 are arranged in astaggered manner with alternating 953 a and 953 b. The connectionterminal 953 is formed on one end of the source signal line, and aterminal electrode for checking is formed on the other end.

Although it has been stated that the IC chip according to the presentinvention is a current-driven driver IC (by which pixels are programmedwith current), this is not restrictive. For example, the presentinvention is also applicable to EL display panels (apparatus) equippedwith a voltage-driven driver IC by which pixels are programmed withvoltage as shown in FIGS. 43, 53, etc.

The anode wires 952 (anode wiring after branching) are placed betweenthe connection terminals 953 a and 953 b. That is, the anode wires 952branching off from the thick, low-resistance base anode line 951 isformed between the connection terminals 953 and laid along the pixel 16columns. Thus, the anode wires 952 and source signal lines 18 are formed(placed) in parallel. This configuration (formation) makes it possibleto apply the voltage Vdd to each pixel without routing the base anodeline 951 to the side of the screen as shown in FIG. 105.

FIG. 96 further illustrates this more concretely. FIG. 96 differs fromFIG. 95 in that instead of being placed between the connection terminals953, the anode wires branch off from a common anode line 962 formedseparately. The common anode line 962 is connected to the base anodeline 951 by connection anode lines 961.

FIG. 96 illustrates the back surface of the IC chip 14 as seen throughthe IC chip 14. The IC chip 14 contains current output circuits 704which output programming current Iw to output terminals 761. Basically,the output terminals 761 and current output circuits 704 are arrangedorderly. In the center of the IC chip 14, there are a circuit whichgenerates basic current for a parent current source and a controlcircuit. Thus, no output terminal 761 is formed in the center of the ICchip 14. This is because no current output circuit 704 can be formed inthe center of the IC chip 14.

According to the present invention, in the high-current-region currentoutput circuit 704 a part in FIG. 96, any output terminals 761 are notprovided with the IC chip, because there is no output circuit.Incidentally, it is often the case that although a control circuit isformed, no output circuit is formed in the center of an IC chip such asa source driver. In view of this, the present invention does not form(place) any output terminal 761 in the center of the IC chip 14. Ofcourse, it is not the case when forming (placing) output terminals 761in the center of the IC chip 14.

According to the present invention, connection anode lines 961 areformed in the center of the IC chip 14. Needless to say, however, theconnection anode lines 961 are formed on a surface of the array board71. The width of the connection anode lines 961 is between 50 and 1000μm (both inclusive) Also, the resistance (the maximum resistance) withrespect to the length should be 100 Ω or less.

The base anode line 951 and common anode line 962 should beshort-circuited by the connection anode lines 961 to minimize voltagedrops caused by current flowing through the common anode line 962. Thatis, the connection anode lines 961, which are a component of the presentinvention, take advantage of the absence of output circuits in thecenter of the IC chip. By removing output terminals 761 conventionallyformed as dummy pads in the center of the IC chip, the present inventionprevents electrical effects which would be caused if the dummy padscontact the connection anode lines 961.

However, if the dummy pads are electrically insulated from a basesubstrate of the IC chip (ground of the chip) or other structure, thereis no problem at all even if the dummy pads contact the connection anodelines 961. Thus, needless to say, the dummy pads may also be formed inthe center of the IC chip.

More specifically, the connection anode lines 961 and common anode line962 are formed (placed) as shown in FIG. 99. To begin with, a connectionanode line 961 has a thick part (961 a) and thin part (961 b). The thickpart (961 a) is intended to reduce resistance value. The thin part (961b) is used to form a connection anode line 961 b between outputterminals 963 and connect it to the common anode line 962.

The base anode line 951 and common anode line 962 are short-circuitednot only via the central connection anode line 961 b, but also via theright and left connection anode lines 961 c. That is, the common anodeline 962 and base anode line 951 are short-circuited by three connectionanode lines 961. With this configuration, the common anode line 962 areless prone to voltage drops even if a large current flows through thecommon anode line 962. This is because the IC chip 14 is normally 2 mmor more in width, making it possible to increase the line width(decrease the impedance) of the base anode line 951 formed under the IC14. Consequently, the low-impedance base anode line 951 and common anodeline 962 are shorted by the connection anode lines 961 at a fewlocations, reducing voltage drops in the common anode line 962.

The voltage drops in the common anode line 962 can be reduced in thisway, because the base anode line 951 can be placed (formed) under the ICchip 14, the connection anode lines 961 c can be placed (formed) on leftand right of the IC chip 14, and the connection anode line 961 b can beplaced (formed) in the center of the IC chip 14.

Also, in FIG. 99, the base anode line 951 and a cathode power line (basecathode line) 991 are laminated with an insulating film 102 placedbetween them. The laminate constitutes a capacitor. This architecture isreferred to as an anode capacitor architecture. This capacitor functionsas a power path capacitor. Thus, sharp current changes in the base anodeline 951 can be absorbed. If the display area of an EL display apparatusis S square millimeters and the capacitance of a capacitor is C (pF),preferably the capacitance of the capacitor satisfies M/200≦C≦M/10 orless. More preferably, it satisfies M/100≦C≦M/20 or less. A small Cmakes it difficult to absorb current changes, but too large C makes theformation area of the capacitor too large and is not practical.

Incidentally, it has been stated in the example in FIG. 99 and the likethat the base anode line 951 is placed (formed) under the IC chip 14,and needless to say, this also applies to the cathode line. Also, inFIG. 99, the base anode line 951 may be replaced with the base cathodeline 991. A technical idea of the present invention lies in constructinga driver from a semiconductor chip, mounting the semiconductor chip onan array board 71 or a flexible board, and placing (forming) wiring onthe back surface of the semiconductor chip to supply power or groundpotential (current) to EL elements 15, etc.

Thus, the semiconductor chip may be not only a source driver IC 14, butalso a gate driver circuit 12 or power supply IC. Also, the technicalidea of the present invention includes mounting a semiconductor chip ona flexible board and laying (forming) a power supply or ground patternfor EL elements 15 or the like in a space on the flexible board and onthe back of the semiconductor chip. Of course, both source driver IC 14and gate driver IC 12 may be constructed of semiconductor chips andmounted on the array board 71 by COG. Then, the power supply or groundpattern may be formed on the back surface of the chips. Also, althoughit has been stated that the power supply or ground pattern is intendedfor the EL elements 15, this is not restrictive and the power supply maybe intended for the source driver circuit 4 or gate driver circuit 12.Besides, the technical idea of the present invention applies not only toEL display apparatus, but also to liquid crystal display apparatus. Itis also applicable to FED, PDP, and other display panels. The aboveitems are also true to other examples of the present invention.

FIG. 97 shows another example of the present invention. FIG. 97 differsfrom FIGS. 95, 96, and 99 mainly in that in FIG. 97, a large number ofthin connection anode lines 961 d branch off from the base anode line951, short-circuiting to the common anode line 962 whereas in FIG. 95,the anode wires 952 are placed between the connection terminals 953.Also, the thin connection anode lines 961 d and source signal lines 18connected with the connection terminals 953 are laminated with aninsulating film 102 placed between them.

The anode lines 961 d are connected with the base anode line 951 incontact holes 971 a while the anode wires 952 are connected with thecommon anode line 962 in contact holes 971 b. In other respects (theconnection anode lines 961 a, 961 b, 961 c and anode capacitor, etc.),FIG. 97 is similar to FIGS. 96 and 99, and thus description thereof willbe omitted.

FIG. 98 shows a sectional view taken along line a-a′ in FIG. 99. In FIG.98(a), a source signal line 18 and connection anode line 961 d ofapproximately the same width are laminated with an insulating film 102 aplaced between them. Preferably, the thickness of the insulating film102 a is between 500 and 3000 Angstrom (Å) both inclusive. Morepreferably, it is between 800 and 2000 Angstrom (Å) both inclusive.Small film thickness is not desirable because it will increase parasiticcapacitance in the connection anode line 961 d and source signal line 18and tend to cause a short circuit between the connection anode line 961d and source signal line 18. On the other hand, thick film thicknesswill cause insulating-film formation to take time, resulting in longmanufacturing time and high cost. Also, wiring on the upper side becomesdifficult.

Possible materials for the insulating film 102 include, for example,organic materials such as polyvinyl alcohol (PVA) resin, epoxy resin,polypropylene resin, phenol resin, acrylic resin, polyimide resin aswell as inorganic materials such as SiO2 and SiNx. Needless to say,A123, Ta203, and the like are also included in the possible materials.Also, as illustrated in FIG. 98(a), an insulating film 102 b is formedin the outermost layer to protect the wiring 961 and the like fromcorrosion and mechanical damage.

In FIG. 98(b), a connection anode line 961 d thinner than a sourcesignal line 18 is placed on top of the source signal line 18 with aninsulating film 102 a placed between them. This configuration preventssteps in the source signal line 18 from causing a short-circuit betweenthe source signal line 18 and connection anode line 961 d. In theconfiguration shown in FIG. 98(b), preferably the width of theconnection anode line 961 d is thinner than that of the source signalline 18 by 0.5 μm or more. More preferably, the connection anode line961 d is thinner than the source signal line 18 by 0.8 μm or more.

Although it has been stated with reference to FIG. 98(b) that theconnection anode line 961 d thinner than the source signal line 18 isplaced on top of the source signal line 18 with an insulating film 102 aplaced between them, it is also possible to place a source signal line18 thinner than a connection anode line 961 d on top of the connectionanode line 961 d with an insulating film 102 a placed between them asillustrated in FIG. 98(c). Other items are the same as in otherexamples, and thus description thereof will be omitted.

FIG. 100 shows a sectional view of an IC chip 14. Basically, thisconfiguration is based on the configuration in FIG. 99, but it issimilarly or analogously applicable to FIGS. 96, 97, etc.

FIG. 100(b) shows a sectional view taken along line A-A′ in FIG. 99. Ascan be seen from FIG. 100(b), no output pad 761 is formed (placed) inthe center of the IC chip 14. The output pads are connected with thesource signal lines 18 of the display panel. A bump is formed on theoutput pads 761 by a plating technique or ball bonding technique. Thebump should be 10 to 40 μm high (both inclusive). Of course, it goeswithout saying that the bump may be formed by a gold plating technique(electrolytic or electroless).

The bumps and the source signal lines 18 are connected electrically viaa conductive bonding layer (not shown). The conductive bonding layer ismade of an epoxy or phenolic base resin mixed with flakes of silver(Ag), gold (Au), nickel (Ni), carbon (C), tin oxide (SnO2), and thelike, or made of an ultraviolet curing resin. The conductive bondinglayer (bonding resin) 1001 is formed on the bump by a transfer or othertechnique. Also, the bumps and the source signal lines 18 are bonded bythermocompression using an ACF resin 1001.

Incidentally, the techniques for connecting the bumps or output pads 761with the source signal lines 18 are not limited to those describedabove. Besides, a film carrier technique may be used instead of mountingthe IC 14 on the array board. Also, polyimide films or the like may beused for connection with the source signal lines 18. FIG. 100(a) is asectional view of a part where a source signal line 18 and the commonanode line 962 overlap (see FIG. 98).

Anode wires 952 branch off from the common anode line 962. There are 528(=176×RGB) anode wires 952 in a QCIF panel. The voltage Vdd (anodevoltage) illustrated in FIG. 1 and the like is supplied via the anodewires 952. A current of up to 200 μA flows through one anode wire 952 ifthe EL elements 15 are made of low molecular weight-material. Therefore,a current of approximately 100 mA (200 μA×528) flows through the commonanode line 962.

Thus, to maintain voltage drops in the common anode line 962 at 0.2 (V)or below, the maximum resistance value of paths through which thecurrent flows must be maintained at or below 2 Ω (assuming that acurrent of 100 mA flows). According to the present invention, since theconnection anode lines 961 are formed at three locations as shown inFIG. 99, the resistance value of the common anode line 962 can easily beminimized in design in terms of a concentrated distribution circuit. Ifa large number of connection anode lines 961 d are formed as shown inFIG. 97, voltage drops in the common anode line 962 can almost beeliminated.

A problem is the effect of parasitic capacitance (referred to as commonanode parasitic capacitance) in portions where the common anode line 962and source signal lines 18 overlap. Basically, in current driving,presence of parasitic capacitance in source signal lines 18 makes itdifficult to write black display current into the source signal lines18. Thus, parasitic capacitance needs to be minimized.

The common anode parasitic capacitance must not be larger than 1/10 ofparasitic capacitance (referred to as display parasitic capacitance)generated by one source signal line 18 in a display area. For example,if the display parasitic capacitance is 10 (pF), the anode parasiticcapacitance must be 1 (pF) or less. More preferably, the anode parasiticcapacitance is not larger than 1/20 of the display parasiticcapacitance. If the display parasitic capacitance is 10 (pF), the anodeparasitic capacitance must be 0.5 (pF) or less. The line width (M inFIG. 103) of the common anode line 962 and the film thickness of theinsulating film 102 (see FIG. 101) are determined by taking this pointinto consideration.

The base anode line 951 is formed (placed) under the IC chip 14.Needless to say, its line width should be as thick as possible to reduceresistance. Besides, preferably the base anode line 951 is provided witha light shielding function.

An explanatory diagram is shown in FIG. 102. Needless to say, if thebase anode line 951 is formed of a metal material to a required filmthickness, it will have a light shielding function. If the base anodeline 951 cannot be made thick enough or is made of transparent materialsuch as ITO, light-absorbing film or light-reflecting film is stacked ina single or multiple layers under the IC chip 14 and on the base anodeline 951 (basically, on the surface of the array board 71). Thelight-shielding film (base anode line 951) in FIG. 102 does not need toshield light perfectly. It may have openings. Also, it may havediffraction effect or scattering effect. Also, light-shielding filmconsisting of multilayer optical interference film may be formed orplaced by stacking on the base anode line 951.

Of course, a reflector plate (sheet) or light-absorbing plate (sheet)made of a metal foil, plate, or sheet may be placed, inserted or formedin the space between the array board 71 and IC chip 14. Needless to say,it is also possible to place, insert or form a reflector plate (sheet)or light-absorbing plate (sheet) made of a foil, plate or sheet oforganic or inorganic material rather than a metal foil. Alternatively,light-absorbing material or light-reflecting material in a gel or liquidstate may be inserted or formed in the space between the array board 71and IC chip 14. Preferably, light-absorbing material or light-reflectingmaterial in the gel or liquid state are solidified by heating or byexposure to light. Incidentally, it is assumed for ease of explanationthat the base anode line 951 is made of a light-shielding film(light-reflecting film).

As shown in FIG. 102, the base anode line 951 is formed on the surfaceof the array board 71 (not limited to the surface). The idea of alight-shielding film or light-reflecting film can be satisfied if lightdoes not reach the rear surface of the IC chip 14. Thus, needless tosay, the base anode line 951 and the like may be formed on an innersurface or inner layer of the array board 71. Alternatively, the baseanode line 951 (an arrangement or structure which functions as areflecting film or light-shielding film) may be formed on the rearsurface of the array board 71 as long as it can prevent or reduceentrance of light into the IC 14.

Although it has been stated with reference to FIG. 102 and the like thatthe light-shielding film and the like are formed on the array board 71,this is not restrictive and the light-shielding film and the like may beformed directly on the rear surface of the IC chip 14. In that case, aninsulating film 102 (not shown) is formed on the rear surface of the ICchip 14 and the light-shielding film, reflecting film, or the like isformed on the insulating film. When forming the source driver circuit 14directly on the array board 71 (driver construction by low-temperaturepolysilicon technology, high-temperature polysilicon technology,solid-phase growth technology, or amorphous silicon technology), thesource driver circuit 14 can be formed (placed) on the light-shieldingfilm, light-absorbing film, or reflecting film which is formed on thearray board 71.

A large number of transistor elements, such as current sources 634,which pass minute current are formed on the IC chip 14 (circuit formingsection 1021 in FIG. 102). When light enters transistor elements (suchas unit transistors 634) which pass minute current, a photoconductionphenomenon and the like occur, making values of output current(programming current Iw), parent current, child current, etc. abnormal(causing variations, and the like). In the case of organic EL or otherself-luminous elements, in particular, light produced by the EL elements15 is reflected diffusely within the array board 71, causing intenselight to be radiated from places other than the display screen 50. Theradiated light, upon entering the circuit forming section 1021 of the ICchip 14, causes the photoconduction phenomenon. Thus, measures againstthe photoconduction phenomenon are measures against a problem peculiarto EL display devices.

To deal with this problem, the present invention constructs the baseanode line 951 on the array board 71 and uses it as a light-shieldingfilm. The formation area of the base anode line 951 covers the circuitforming section 1021 as illustrated in FIG. 102. By forming thelight-shielding film (base anode line 951) in this way, it is possibleto prevent the photoconduction phenomenon completely. As the screen isrefreshed, current flows through EL power lines such as the base anodeline 951, in particular, causing some changes to their potential.However, since the potential changes little by little every horizontalscanning period, it can be regarded as ground potential (meaning thatthere is virtually no change in the potential). Thus, the base anodeline 951 or base cathode line performs not only a light-shieldingfunction, but also an electric shielding function.

In the case of organic EL or other self-luminous elements, lightproduced by the EL elements 15 is reflected diffusely within the arrayboard 71, causing intense light to be radiated from places other thanthe display screen 50. To prevent or reduce the diffusely reflectedlight, light-absorbing films 1011 are formed in ineffective areas whichdo not pass light effective for image display as illustrated in FIG. 101(on the other hand, effective areas are the display screen 50 and areasaround it). The light-absorbing films are formed on an outer surface ofa sealing lid 85 (light-absorbing film 1011 a), inner surface of thesealing lid 85 (light-absorbing film 1011 c), side face of the board 70(light-absorbing film 1011 d), area on the board other than the imagedisplay area (light-absorbing film 1011 b), etc. Incidentally, insteadof light-absorbing films, light-absorbing sheets or light-absorbingwalls may be installed. Besides, the concept of light absorption alsoincludes schemes or structures which diverge light by scattering it. Ina broader sense, it also includes schemes or structures which confinelight through reflection.

Possible materials for light-absorbing films include, for example,organic material such as acrylic resin containing carbon, organic resinwith a black pigment dispersed in it, and gelatin or casein colored witha black acidic dye as with a color filter. Besides, they also include afluorine-based pigment which singly develops a black color as well asgreen and red pigments which develop a black color when mixed.Furthermore, they also include PrMnO3 film formed by sputtering,phthalocyanine film formed by plasma polymerization, etc.

All the above materials develop black colors, but materials whichdevelop a color complementary to the color developed by display elementsmay also be used for the light-absorbing films. For example,light-absorbing materials for color filters can be used by modifyingthem so as to provide desired light-absorbing characteristics.Basically, natural resin colored by dyes may be used as is the case withthe black light-absorbing materials described above. It is also possibleto use plastics in which dyes are dispersed. In that case, an availablerange of pigments is wider than in the case of black pigments andincludes azo dyes, anthraquinone dyes, phthalocyanine dyes, andtriphenylmethane dyes. An appropriate one of them or a combination oftwo or more of them may be used.

Besides, metal materials may also be used for the light-absorbing films.Possible materials include, for example, hexavalent chromium. Hexavalentchromium is black in color and functions as a light-absorbing film.Besides, light-scattering materials such as opal glass and titaniumoxide are also available. By scattering light, it is often possible toabsorb light as a result.

Incidentally, the sealing lid 85 is bonded to the array board 71 using asealing resin 1031 containing resin beads 1012 from 4 μm to 15 μm (bothinclusive) in diameter. The sealing lid 85 is placed without applyingpressure and fixed.

The example illustrated in FIG. 99 involves forming (placing) the commonanode line 962 near the IC chip 14, but this is not restrictive. Forexample, the common anode line 962 may be formed near the display screen50 as illustrated in FIG. 103. Rather, this is preferable because thiswill reduce parts where the source signal lines 18 and anode wires 952are placed at short distances in parallel with each other. If the sourcesignal lines 18 and anode wires 952 are placed at short distances inparallel with each other, parasitic capacitance will be produced betweenthem. This problem can be solved if the common anode line 962 is placednear the display screen 50 as illustrated in FIG. 103. Preferably, thedistance K (see FIG. 103) from the display screen 50 to the common anodeline 962 is 1 mm or less.

Preferably, the common anode line 962 is made of the same metal materialas the source signal lines 18 to minimize its resistance. According tothe present invention, it is made of metal material (SD metal) such asthin Cu film, thin Al film, Ti/Al/Ti laminate, alloy, or amalgam. Thus,this material is replaced by the same metal material (GE metal) as thegate signal lines 17 at intersections of the source signal lines 18 andcommon anode line 962 to prevent short circuits. The gate signal linesare made of metal material, namely a Mo/W laminate.

Generally, the sheet resistance of gate signal lines 17 is higher thanthe sheet resistance of source signal lines 18. This is common to liquidcrystal display apparatus. However, in organic EL display panels of acurrent-driving type, the current flowing through source signal lines 18is as weak as 1 to 5 μA. Thus, even if the source signal lines 18 have ahigh resistance, almost no voltage drop occurs, and thus proper imagedisplay can be achieved. In liquid crystal display apparatus, image datais written into the source signal lines 18 by way of voltage. Thus, ifthe source signal lines 18 have a high resistance value, it is notpossible to write images in one horizontal scanning period.

With the current driving according to the present invention, however, ahigh resistance value (i.e., a high sheet resistance value) of thesource signal lines 18 does not pose a problem. Therefore, the sheetresistance of the source signal lines 18 may be higher than the sheetresistance of the gate signal lines 17. Thus, in the EL display panel ofthe present invention, the source signal lines 18 may be made (formed)of GE metal and the gate signal lines 17 may be made (formed) of SDmetal as illustrated in FIG. 104 (contrary to liquid crystal displaypanels). In a broader sense, in the EL display panel of acurrent-driving type, the wiring resistance of the source signal lines18 is higher than the wiring resistance of the gate signal lines 17.

A configuration in FIG. 107 contains power wiring 1051 for driving gatedriver circuits 12 in addition to the configurations in FIGS. 99 and103. The power wiring 1051 is routed from the right edge of the displayscreen 50 through the bottom side to the left edge of the display screen50. That is, gate driver circuits 12 a and 12 b have a common powersupply.

Preferably, however, the gate driver circuit 12 a which selects the gatesignal line 17 a (which controls the selection transistors 11 b and 11c) and gate driver circuit 12 b which selects the gate signal line 17 b(which controls the transistor 11 d and current flowing through the ELelement 15) have different power supply voltages. In particular, it ispreferable that the amplitude (difference between turn-on voltage andturn-off voltage) of the gate signal line 17 a is small. This is becausethe smaller the amplitude of the gate signal line 17 a, the smaller thepenetration voltage to the capacitor 19 in the pixel 16 (see FIG. 1,etc.) On the other hand, the amplitude of the gate signal line 17 bcannot be decreased because the gate signal line 17 b must control theEL element 15.

Thus, as illustrated in FIG. 108, applied voltages of the gate drivercircuit 12 a are Vha (turn-off voltage for the gate signal line 17 a)and Vla (turn-on voltage for the gate signal line 17 a) while appliedvoltages of the gate driver circuit 12 a are Vhb (turn-off voltage forthe gate signal line 17 b) and Vla (turn-on voltage for the gate signalline 17 b). A relationship Vla<Vlb should be satisfied. Incidentally,Vha and Vhb may be approximately equal.

Normally, N-channel transistors and P-channel transistors are used forthe gate driver circuits 12, but preferably, only P-channel transistorsare used. This is because it will reduce the number of masks used infabrication of arrays, increase production yields, and improvethroughput. Thus, as illustrated in FIGS. 1, 2, etc., P-channeltransistors should be used for the pixels 16 as well as for the gatedriver circuits 12. Ten masks are required if N-channel transistors andP-channel transistors are used for a gate driver circuit, but five masksare required if only P-channel transistors are used.

However, if only P-channel transistors are used for the gate drivercircuits 12 and the like, no level shifter circuit can be formed on thearray board 71. This is because level shifter circuits employ N-channeltransistors and P-channel transistors.

To solve this problem, the present invention incorporates level shiftercircuit functions into a power supply IC 1091. FIG. 109 shows an exampleof this. The power supply IC 1091 generates the drive voltage of thegate driver circuits 12, anode voltage and cathode voltage of the ELelements 15, and drive voltage of the source driver circuit 14.

To generate the anode and cathode voltages of the EL elements 15 of thegate driver circuits 12, the power supply IC 1091 needs to employ highvoltage semiconductor processes. Such voltage resistance allows a levelshift to signal voltage of the gate driver circuits 12. Also, asillustrated in FIG. 205, level shifter circuits 2041 may be formed inthe source driver IC 14. The level shifter circuits 2041 may be formedon left and right sides of the source driver IC 14. When using more thanone source driver IC 14 as shown in FIG. 205, one of the level shiftercircuits 2041 in each source driver IC 14 is used.

In FIG. 205, a level shifter circuit 2041 a in a source driver IC 14 ais used. Gate control data is boosted by the level shifter circuit 2041a to become a gate driver control signal 2043 a and controls the gatedriver circuit 12 a. Also, a level shifter circuit 2041 b in a sourcedriver IC 14 b is used. Gate control data is boosted by the levelshifter circuit 2041 b to become a gate driver control signal 2043 b andcontrols the gate driver circuit 12 b.

The configurations in FIG. 109 is used to perform level shifting anddrive the gate driver circuits 12. Input data (image data, commands, andcontrol data) 992 are fed into the source driver IC 14. The input dataalso contains control data of the gate driver circuit 12. The sourcedriver IC 14 has a voltage resistance (operating voltage) of 5 (V). Onthe other hand, the gate driver circuits 12 have an operating voltage of15 (V). The signal outputted from the source driver circuit 14 to thegate driver circuits 12 must be level-shifted from 5 (V) to 15 (V). Thelevel shifting is performed by the power supply circuit (IC) 1091. InFIG. 109, a data signal for use to control the gate driver circuits 12is designated as a power supply IC control signal 1092.

Upon receiving the data signal 1092 for use to control the gate drivercircuits 12, the power supply circuit 1091 level-shifts it with abuilt-in level shifter circuit and outputs the resulting signal as agate driver circuit control signal 1093 to control the gate drivercircuits 12.

Now description will be given of the gate driver circuits 12 accordingto the present invention which are contained in the array board 71 andemploy only P-channel transistors. As described earlier, by employingonly P-channel transistors for the pixels 16 and gate driver circuits 12(i.e., the transistors formed on the array board 71 are only P-channeltransistors, meaning that no N-channel transistor is used), it ispossible to reduce the number of masks used in fabrication of arrays,increase production yields, and improve throughput. Also, since it ispossible to focus on improving performance of only P-channeltransistors, characteristics can be improved easily as a result. Forexample, it is easier to lower threshold voltage (Vt) (bring it closerto 0 (V)) and reduce variations in the Vt than in the case of CMOSstructures (an arrangement using P-channel and N-channel transistors).

To take an example, according to the present invention, one gate drivercircuit 12 each is placed on a phase basis (shift registers), formed orconstructed on the left and right of the display screen 50 asillustrated in FIG. 106. Although it is assumed that gate drivercircuits 12 and the like (including pixel 16 transistors) are formed orconstructed by low-temperature polysilicon technology at a processtemperature of 450 degrees (centigrade) or lower, this is notrestrictive. It is also possible to use transistors produced byhigh-temperature polysilicon technology at a process temperature of 450degrees (centigrade) or higher, or transistors made of CGS semiconductorfilms produced by solid-phase growth. Besides, organic transistors arealso available. Alternatively, transistors may be formed or constructedby amorphous silicon technology.

One of the gate driver circuits 12 is a selection-side gate drivercircuit 12 a. It controls the pixel transistors 11 by applying turn-onvoltage or turn-off voltage to the gate signal lines 17 a. The othergate driver circuit 12 b turns on and off the current passed through theEL elements 15.

Although the examples of the present invention is described by mainlytaking the pixel configuration in FIG. 1 as an example, this is notrestrictive. Needless to say, the present invention is also applicableto other pixel configurations shown in FIGS. 50, 51, 54, etc. Also, theconfiguration or drive system of the gate driver circuits 12 accordingto the present invention produce more characteristic effects if combinedwith the display panel, display apparatus, or information displayapparatus according to the present invention. Needless to say, however,the gate driver circuits 12 can also produce characteristic effects evenwhen other configurations are employed.

Incidentally, the configuration or layout of the gate driver circuit 12described below is not limited to self-luminous devices such as organicEL display panels. It can also be used for liquid crystal displaypanels, electromagnetic display panels, etc. For example, liquid crystaldisplay panels may employ the configuration or arrangement of the gatedriver circuit 12 according to the present invention to control pixels'selection switching elements. If two gate driver circuits 12 are used,one of them may be used to select pixels' switching elements and theother may be connected to one terminal of a retention capacitance ineach pixel. This scheme is referred to as independent CC driving.Needless to say, the configurations described with reference to FIGS.111, 113, etc. can also be used not only for the gate driver circuits12, but also for the shift register circuits and the like, of the sourcedriver circuit 14.

Preferably, the gate driver circuit 12 described here is implemented oradopted as the gate driver circuits 12 described earlier with referenceto FIGS. 6, 13, 16, 20, 22, 24, 26, 27, 28, 29, 34, 37, 40, 41, 48, 82,91, 92, 93, 103, 104, 105, 106, 107, 108, 109, 176, 181, 187, 188, 208,etc.

FIG. 111 is a block diagram of the gate driver circuit 12 according tothe present invention. Although only four stages are illustrated forease of explanation, basically there are formed or placed as many unitgate output circuits 1111 as there are gate signal lines 17.

As illustrated in FIG. 111, the gate driver circuits 12 (12 a and 12 b)according to the present invention comprise signal terminals: four clockterminals (SCK0, SCK1, SCK2, and SCK3), one start terminal (data signal(SSTA)), and two inverting terminals (DIRA and DIRB which apply signals180 degrees out of phase with each other) which turn a shift directionupside down. They also comprise power supply terminals, including an Lpower supply terminal (VBB) and H power supply terminal (Vd).

Since only P-channel transistors are used for the gate driver circuits12 here, no level shifter circuit (circuit used to convert a low voltagelogic signal into a high voltage logic signal) can be incorporated intothe gate driver circuits. Thus, the level shifter circuit is placed orformed in the power supply circuit (IC) 1091 shown in FIG. 109 and thelike.

The power supply circuit (IC) 1091 generates voltages of potentialsneeded for a turn-on voltage (selection voltage of pixel 16 transistors)and turn-off voltage (non-selection voltage of pixel 16 transistors) tobe output from the gate driver circuits 12 to the gate signal lines 17.Consequently, semiconductor processes for the power supply IC (circuit)1091 have sufficient voltage resistance. Thus, the logic signals can belevel-shifted (LS) conveniently by the power supply IC 1091. For thisreason, gate driver circuit 12 control signals outputted from acontroller (not shown) are fed into the power supply IC 1091 andlevel-shifted there before it is fed into the gate driver circuits 12according to the present invention. Source driver circuit 14 controlsignals outputted from the controller (not shown) are fed into thesource driver circuit 14 and the like according to the present inventiondirectly (there is no need for level shifting).

However, the present invention does not limit all the transistors formedon the array board 71 to P-channel transistors. By using only P-channeltransistors for the gate driver circuits 12 as described later withreference to FIGS. 111 and 113, it is possible to reduce bezel width. Inthe case of a 2.2-inch QCIF panel, the width of a gate driver circuit 12can be constructed of 600 μm if a 6-μm rule is adopted. The width willbe 700 μm even including power wiring of the supplying gate drivercircuit 12. If CMOS (N-channel and P-channel transistors) is used for asimilar circuit configuration, the width will be increased to 1.2 mm.Thus, by using only P-channel transistors for the gate driver circuits12, it is possible to achieve a characteristic effect of bezel widthreduction.

Also, if the pixels 16 are constructed of P-channel transistors, theywill match well with the gate driver circuits 12 which employ P-channeltransistors. The P-channel transistors (the selection transistors 11 band 11 c and transistor 11 d in the configuration in FIG. 1) turn onwhen the voltage becomes low. On the other hand, the lower voltageserves as the selection voltage for the gate driver circuits 12 as well.Gate drivers with P-channel achieve good matching if the lower level isused as the selection level as can be seen from a configuration in FIG.113. This is because the lower level cannot be maintained for a longtime. On the other hand, the higher voltage can be maintained for a longtime.

Also, by using P-channel for the driver transistors (transistor 11 a inFIG. 1) which supply current to the EL element 15, it is possible to usea solid electrode made of thin metal film as the cathode of the ELelements 15. Also, current can be passed from the anode potential Vdd tothe EL elements 15 in the forward direction. In view of the abovecircumstances, it is preferable that the transistors in the pixels 16and gate driver circuits 12 are P-channel. Thus, the use of P-channeltransistors as the transistors (driver transistors and itchingtransistors) in the pixels 16 and gate driver circuits 12 according tothe present invention is not merely a design matter.

In this sense, the level shifter (LS) circuit maybe formed directly onthe array board 71. That is, N-channel and P-channel transistors areused for the level shifter (LS) circuit. A logic signal from acontroller (not shown) is boosted by the level shifter circuit formeddirectly on the array board 71 so that it will match the logic level ofthe gate driver circuits 12 constructed from a P-channel transistor. Theboosted logic voltage is applied to the gate driver circuits 12.

Incidentally, the level shifter circuit may be constructed from asemiconductor chip and mounted on the array board 71 using COGtechnology or the like. Also, the source driver circuit 14 isconstructed basically from a semiconductor chip and mounted on the arrayboard 71 using COG technology, as illustrated in FIG. 109 and the like.However, this is not restricted to forming the source driver circuit 14as a semiconductor chip and the source driver circuit 14 may be formeddirectly on the array board 71 using polysilicon technology. IfP-channel transistors are used as the transistors 11 of pixels 16,programming current flows in the direction from the pixels 16 to thesource signal lines 18. Thus, N-channel transistors should be used asthe unit current circuits 634 of the source driver circuits (see FIGS.73 and 74). That is, the source driver circuits 14 should be configuredin such a way as to draw the programming current Iw.

Thus, if the driver transistors 11 a of the pixels 16 (in the case ofFIG. 1) are P-channel transistors, the unit transistors 634 of thesource driver circuits 14 must be N-channel transistors to ensure thatthe source driver circuits 14 will draw the programming current Iw. Inorder to form a source driver circuit 14 on an array board 71, it isnecessary to use both mask (process) for N-channel transistors and mask(process) for P-channel transistors. Conceptually speaking, in thedisplay panel (display apparatus) of the present invention, P-channeltransistors are used for the pixels 16 and gate driver circuits 12 whileN-channel transistors are used as the transistors of drawing currentsources of the source drivers.

Incidentally, for ease of explanation, the pixel configuration in FIG. 1is employed in the example of the present invention. However, thetechnical idea of the present invention which involves the use ofP-channel transistors as selection transistors (transistor 11 c inFIG. 1) of pixels 16 and for gate driver circuits 12 is not limited tothe pixel configuration in FIG. 1. Needless to say, for example, it isalso applicable to the current-mirror pixel configuration illustrated inFIG. 42 in the case of current-driven pixel configuration. Also, it isapplicable to two transistors (selection transistor is transistor 11 band driver transistor is transistor 11 a) such as those illustrated inFIG. 62 in the case of voltage-driven pixel configuration. Of course, itis also applicable to the gate driver 12 configurations in FIGS. 111 and113 and they can be combined to construct an apparatus. Thus, the itemsdescribed above as well as the items described below are not limited topixel configuration or the like.

The configuration in which P-channel transistors are used as selectiontransistors of pixels 16 and for gate driver circuits is not limited toorganic EL or other self-luminous devices (display panels or displayapparatus). For example, it is also applicable to liquid crystal displaypanels and FEDs (field emission displays).

The inverting terminals (DIRA and DIRB) apply common signals to all theunit gate output circuits 1111. As can be seen from an equivalentcircuit diagram in FIG. 113, inverting terminals (DIRA and DIRB) are fedvoltage values of opposite polarity. To reverse the scan direction ofthe shift register, the polarity of the voltage values fed into theinverting terminals (DIRA and DIRB) is reversed.

Incidentally, the circuit configuration in FIG. 111 contains four clocksignal lines. Four is the optimum number according to the presentinvention. However, this is not restrictive and the present inventionmay use less than or more than four clock signal lines.

The clock signals (SCK0, SCK1, SCK2, and SCK3) are fed differentlybetween adjacent unit gate output circuits 1111. For example, in theunit gate output circuit 1111 a, OC is fed by the clock terminal SCK0while RST is fed by the clock terminal SCK2. This is also the case withthe unit gate output circuit 1111 c. However, in the unit gate outputcircuit 1111 b (the unit gate output circuit in the next stage) adjacentto the unit gate output circuit 1111 a, OC is fed by the clock terminalSCK1 while RST is fed by the clock terminal SCK3. In this way, everyother unit gate output circuit 1111 is fed by clock terminals in adifferent manner: OC is fed by SCK0 and RST is fed by SCK2, OC is fed bySCK1 and RST is fed by SCK3 in the next stage, OC is fed by SCK0 and RSTis fed by SCK2 in the next stage, and so on.

FIG. 113 shows a circuit configuration of the unit gate output circuit1111, which uses only P-channel transistors. FIG. 114 is a timing chartfor use to explain the circuit configuration of FIG. 113. FIG. 112 is atiming chart of multiple stages in FIG. 113. Thus, by understanding FIG.113, it is possible to understand overall operation. Rather than beingexplained in text, the operation can be understood with reference to thetiming chart in FIG. 114 in conjunction with the equivalent circuitdiagram in FIG. 113, and thus detailed description of transistoroperation will be omitted.

When driver circuits are built solely of P-channel transistors, it isbasically difficult to maintain the gate signal lines 17 at an H level(Vd voltage in FIG. 113). It is also difficult to maintain them at an Llevel (VBB voltage in FIG. 113) for a long period of time, but they canbe kept adequately at the H level for a short period such as duringselection of a pixel row. A signal fed to an IN terminal and the SCKclock fed to the RST terminal invert the state of n1 with respect to n2.Although n2 and n4 have potentials of the same polarity, the SCK clockfed to the OC terminal lowers the potential level of n4 further. Incontrast, a Q terminal is kept at the L level for the same period (aturn-on voltage is output from the gate signal line 17). A signaloutputted to an SQ terminal or the Q terminal is transferred to the unitgate output circuit 711 in the next stage.

In the circuit configuration in FIGS. 111 and 113, by controlling the IN(INA and INB) terminals and the timings of signal application to clockterminals, it is possible to two modes using the same circuitconfiguration: a mode in which one gate signal line 17 is selected asshown in FIG. 115(a) and a mode in which two gate signal lines 17 areselected as shown in FIG. 115(b).

In the selection-side gate driver circuit 12 a, FIG. 115(a) shows adrive mode in which pixel rows are selected one (51 a) at a time (normaldriving) shifting on a row-by-row basis. FIG. 115(b) shows aconfiguration in which two pixel rows are selected at a time. This drivemode corresponds to the driving for simultaneous selection of multiplepixel rows (51 a and 51 b) described with reference to FIGS. 27 and 28(configuration in which a dummy pixel row is used). Two adjacent rowsare selected at a time shifting on a row-by-row basis. According to thedrive method in FIG. 115(b) in particular, while the pixel row (51 a)holds final video, the pixel row 51 b is precharged. This makes thepixel 16 easier to write into. That is, the present invention can switchbetween two drive modes by manipulating signals applied to terminals.

Incidentally, although 115(b) shows a mode in which adjacent rows ofpixels 16 are selected as shown in FIG. 116, it is also possible toselect rows of pixels 16 other than adjacent pixel rows (FIG. 116 showsan example in which pixel rows three pixel rows apart are selected). Inthe configuration shown in FIG. 113, pixel rows are controlled in setsof four. Out of four pixel rows, it is possible to determine whether toselect one pixel row or two consecutive pixel rows. The number of pixelrows in each set is restricted by the number of clocks (SCK), which isfour in this case. If eight clocks (SCK) are used, pixel rows can becontrolled in sets of eight.

Operation of the selection-side gate driver circuit 12 a is shown inFIG. 115. In FIG. 115(a), one pixel row is selected at a time andselection position is shifted by one pixel row in sync with a horizontalsynchronization signal. In FIG. 115(b), two pixel rows are selected at atime and selection position is shifted by one pixel row in sync with ahorizontal synchronization signal.

As illustrated in FIG. 182, connection anode lines 961 are wired from ananode connection terminal 1821 and the connection anode lines 961 formedon both sides of a source driver IC 14 are connected electrically bymeans of a switch 2021 formed under the IC 14.

A common anode line 962 is formed or placed on the output side of thesource driver IC 14. Anode wires 952 branch off from the common anodeline 962. There are 528 (=176×RGB) anode wires 952 in a QCIF panel. Thevoltage Vdd (anode voltage) illustrated in FIG. 1 and the like issupplied via the anode wires 952. A current of up to on the order of 200μA flows through one anode wire 952 if the EL elements 15 are made oflow molecular weight-material. Therefore, a current of approximately 100mA (200 μA×528) flows through the common anode wire 833.

To reduce voltage drops in the common connection anode lines 961 andanode wires 952, it is recommended to form a common connection anodeline 961 a on the upper side of the display screen 50, form a commonconnection anode line 961 b on the lower side of the display screen 50,and short-circuit the anode wires 952 at its top and bottom asillustrated in FIG. 183.

It is also preferable to place source driver circuits 14 at the top andbottom of the screen 50 as illustrated in FIG. 184. It is also possibleto divide the display screen 50 into a display screen 50 a and displayscreen 50 b and drive the display screen 50 a with a source drivercircuit 14 a, and the display screen 50 b with a source driver circuit14 b as illustrated in FIG. 185.

FIG. 201 is a block diagram of the power supply circuit according to thepresent invention. Reference numeral 2012 denotes a control circuit,which controls the midpoint potential of resistances 2015 a and 2015 band outputs a gate signal of a transistor 2016. A power supply Vpc isapplied to the primary side of a transformer 2011 and primary current istransmitted to the secondary side under on/off control of the transistor2016. Reference numeral 2013 denotes a rectifying diode and 2014 denotesa smoothing capacitor.

Anode voltage Vdd has its output voltage adjusted to a resistor 2015 b.Vss denotes cathode voltage. One of two voltages can be outputselectively as the cathode voltage Vss as illustrated in FIG. 202.Switch 2021 is used for the selection. In FIG. 202, −9 (V) is selectedby the switch 2021.

The switch 2021 is operated according to output from a temperaturesensor 2022. When panel temperature is low, −9(V) is selected as thevoltage Vss. When the panel temperature is equal to or higher than acertain level, −6(V) is selected. This is because EL elements 15 havetemperature dependence and terminal voltage of the EL elements 15becomes higher on a low temperature side. Incidentally, although it hasbeen stated with reference to FIG. 202 that one of two voltages isselected as Vss (the cathode voltage), this is not restrictive and thevoltage Vss may be selected from three voltages. The above itemssimilarly apply to Vdd.

By allowing a voltage to be selected from a plurality of voltages basedon panel temperature as shown in FIG. 202, it is possible to reducepower consumption of the panel. This is because the voltage Vss can belowered when the temperature is equal to or lower than a certain level.Normally, the lower Vss (=−6(V)) can be used. Incidentally, the switch2021 may be configured as illustrated in FIG. 202. A plurality ofvoltages Vss can be generated easily by using intermediate taps of atransformer 2011 in FIG. 202. This similarly applies to the anodevoltage Vdd.

FIG. 205 is an explanatory diagram illustrating potential setting. Thesource driver IC 14 is based on GND. The power supply for the sourcedriver IC 14 is Vcc. Vcc may be brought to coincide with the anodevoltage (Vdd). According to the present invention, Vcc<Vdd from theviewpoint of power consumption.

The turn-off voltage Vgh of the gate driver 12 is set to equal to orhigher than the voltage Vdd. Preferably, Vdd+0.5 (V)<Vgh<Vdd+2.5 (V) issatisfied. The turn-on voltage Vgl may be brought to coincide with Vss,but preferably Vss(V)<Vgl<−0.5 (V) is satisfied.

It is important to take measures against heat generation from the ELdisplay panel. As a measure against heat generation, a chassis 2062 madeof metal material is mounted on the back of the panel (the side oppositeto the illuminating surface of the display screen 50) as illustrated inFIG. 206. For better heat dissipation, the chassis 2062 is provided withprojections and depressions 2063. Also, a bonding layer is placedbetween the chassis 2061 and panel (the sealing lid 85 in the case ofFIG. 206). A material with good thermal conductivity is used for thebonding layer. Possible materials include, for example, silicone-resinpaste and silicone paste. These materials are often used as an adhesivebetween a regulator IC and radiator plate. Incidentally, it is notstrictly necessary for the bonding layer to have a bonding function aslong as it serves the function of keeping the chassis 2061 and panel inintimate contact with each other.

Holes 2071 are provided in the back surface of the chassis 2062 asillustrated in FIG. 207(a). The holes 2071 are provided to releaseexcess resin when the chassis 2062 and panel are bonded together. Also,the shape of the holes is varied between the center and periphery of thepanel as shown in FIG. 207(a) to adjust thermal resistance of thechassis 2062, and thereby make the panel temperature uniform. In FIG.207(a), the holes 2071 c in the periphery of the panel are made largerthan the holes 2071 a in the center of the panel, thereby increasing thethermal resistance on the periphery of the panel. Consequently, theperiphery of the panel is less liable to heat loss. This allows uniformheat distribution over the entire panel surface. Incidentally, the holes2071 may be circular or the like as illustrated in FIG. 207(b).

FIG. 208 illustrates a configuration of the display panel according tothe present invention. A flexible board 84 is mounted on one side of thearray board 71. A power supply circuit 82 and the flexible board 84 areplaced on the flexible board. FIG. 209 shows a sectional view takenalong line A-A′ in FIG. 208. However, in FIG. 209, the flexible board 84has been bent and the chassis 2062 has been mounted. As can be seen fromFIG. 209, the transformer 2011 of the power supply circuit 82 iscontained in a space provided in the sealing lid 85. This makes itpossible to reduce the thickness of the EL display panel (EL displaypanel module)

Next, description will be given of examples of display devices accordingto the present invention which run the drive systems according to thepresent invention. FIG. 57 is a plan view of a cell phone which is anexample of an information terminal. An antenna 571, numeric keys 572,etc. are mounted on a casing 573. Reference numerals 572 and the likedenote a display color switch key, power key, and frame rate switch key.

The numeric key 572 may be configured to switch among color modes asfollows: pressing it once enters 8-color display mode, pressing it againenters 4096-color display mode, and pressing it again enters260,000-color display mode. The key is a toggle switch which switchamong color display modes each time it is pressed. Incidentally, adisplay color change key may be provided separately. In that case, three(or more) numeric keys 572 are needed.

In addition to a push switch, the numeric key 572 may be a slide switchor other mechanical switch. Speech recognition may also be used forswitching. For example, the switch may be configured such that displaycolors on the display screen 50 of the display panel will change as theuser speaks a phrase such as “high-definition display,” “4096-colormode,” or “low-color display mode” into the phone. This can beimplemented easily using existing speech recognition technology.

Also, display colors may be switched electrically. It is also possibleto employ a touch panel which allows the user to make a selection bytouching a menu presented on the display part 21 of the display panel.Besides, display colors may be switched based on the number of times theswitch is pressed or based on a rotation or direction as is the casewith a click ball.

A key which changes frame rate or a key which switches between movingpictures and still pictures many be used in place of the display colorswitch key 572. A key may switch two or more items at the same time: forexample, among frame rates and between moving pictures and stillpictures. Also, the key may be configured to change the frame rategradually (continuously) when pressed and held. For that, among acapacitor C and a resistor R of an oscillator, the resistor R can bemade variable or replaced with an electronic regulator. Alternatively, atrimmer capacitor may be used as a capacitor C of the oscillator. Such akey can also be implemented by forming a plurality of capacitors in asemiconductor chip, selecting one or more capacitors, and connecting thecapacitors in parallel.

Furthermore, embodiments which use the EL display panel, EL displayapparatus, or drive method according to the present invention will bedescribed with reference to drawings.

FIG. 58 is a sectional view of a viewfinder according to an embodimentof the present invention. It is illustrated schematically for ease ofexplanation. Besides, some parts are enlarged, reduced, or omitted. Forexample, an eyepiece cover is omitted in FIG. 58. The above items alsoapply to other drawings.

Inner surfaces of a casing 573 are dark- or black-colored. This is toprevent stray light emitted from an EL display panel (EL displayapparatus) 574 from being reflected diffusely inside the casing 573 andlowering display contrast. A phase plate (λ/4) 108, polarizing plate109, and the like are placed on an exit side of the display panel. Thishas also been described with reference to FIGS. 10 and 11.

An eye ring 581 is fitted with a magnifying lens 582. The observerfocuses on a display image 50 on the display panel 574 by adjusting theposition of the eye ring 581 in the casing 573.

If a convex lens 583 is placed on the exit side of the display panel 574as required, principal rays entering the magnifying lens 582 can be madeto converge. This makes it possible to reduce the diameter of themagnifying lens 1582, and thus reduce the size of the viewfinder.

FIG. 59 is a perspective view of a video camera. A video camera has ataking (imaging) lens 592 and a video camera casing 573. The taking lens592 and the casing (viewfinder) 573 are mounted back to back with eachother. The viewfinder 573 (see also FIG. 58) is equipped with aneyepiece cover. The observer views the image 50 on the display panel 574through the eyepiece cover.

The EL display panel according to the present invention is also used asa display monitor. The display screen 50 can pivot freely on a point ofsupport 591. The display screen 50 is stored in a storage compartment593 when not in use.

A switch 594 is a changeover switch or control switch and performs thefollowing functions. The switch 594 is a display mode changeover switch.The switch 594 is also suitable for cell phones and the like. Now thedisplay mode changeover switch 594 will be described.

The drive methods according to the present invention include the onethat passes an N times larger current through EL elements 15 toilluminate them for a period equal to 1/M of 1F. By varying thisillumination period, it is possible to change brightness digitally. Forexample, designating that N=4, a four times larger current is passedthrough the EL elements 15. If the illumination period is 1/M, byswitching M among 1, 2, 3, and 4, it is possible to vary brightness from1 to 4 times. Incidentally, M may be switched among 1, 1.5, 2, 3, 4, 5,6, and so on.

The switching operation described above is used for cell phones, whichdisplay the display screen 50 very brightly at power-on and reducedisplay brightness after a certain period to save power. It can also beused to allow the user to set a desired brightness. For example, thebrightness of the screen is increased greatly outdoors. This is becausethe screen cannot be seen at all outdoors due to bright surroundings.However, the EL elements 15 deteriorate quickly under conditions ofcontinuous display at high brightness. Thus, the screen 50 is designedto return to normal brightness in a short period of time if it isdisplayed very brightly. A button which can be pressed to increasedisplay brightness should be provided, in case the user wants to displaythe screen 50 at high brightness again.

Thus, it is preferable that the user can change display brightness withthe switch 594, that the display brightness can be changed automaticallyaccording to mode settings, or that the display brightness can bechanged automatically by detecting the brightness of extraneous light.Preferably, display brightness settings such as 50%, 60%, 80%, etc. areavailable to the user.

Preferably, the display screen 50 employs Gaussian display. That is, thecenter of the display screen 50 is bright and the perimeter isrelatively dark. Visually, if the center is bright, the display screen50 seems to be bright even if the perimeter is dark. According tosubjective evaluation, as long as the perimeter is at least 70% asbright as the center, there is not much difference. Even if thebrightness of the perimeter is reduced to 50%, there is almost noproblem. The self-luminous display panel according to the presentinvention generates a Gaussian distribution from top to bottom of thescreen using the N-fold pulse driving described above (a method whichpasses an N times larger current through EL elements 15 to illuminatethem for a period equal to 1/M of 1F).

Specifically, the value of M is increased in upper and lower parts ofthe screen and decreased in the center of the screen. This isaccomplished by modulating the operating speed of a shift register ofthe gate driver circuits 12. The brightness at the left and right of thescreen is modulated by multiplying video data by table data. By reducingperipheral brightness (at an angle of view of 0.9) to 50% through theabove operation, it is possible to reduce power consumption by 20%compared to brightness of 100%. By reducing peripheral brightness (at anangle of view of 0.9) to 70%, it is possible to reduce power consumptionby 15% compared to brightness of 100%.

Preferably a changeover switch is provided to enable and disable theGaussian display. This is because the perimeter of the screen cannot beseen at all outdoors if the Gaussian display is used. Thus, it ispreferable that the user can change display brightness with the buttonswitch, that the display brightness can be changed automaticallyaccording to mode settings, or that the display brightness can bechanged automatically by detecting the brightness of extraneous light.Preferably, display brightness settings such as 50%, 60%, 80%, etc. areavailable to the user.

Liquid crystal display panels generate a fixed Gaussian distributionusing a backlight. Thus, they cannot enable and disable the Gaussiandistribution. The capability to enable and disable Gaussian distributionis peculiar to self-luminous display devices.

A fixed frame rate may cause interference with illumination of an indoorfluorescent lamp or the like, resulting in flickering. Specifically, ifthe EL elements 15 operate on 60-Hz alternating current, a fluorescentlamp illuminating on 60-Hz alternating current may cause subtleinterference, making it look as if the screen were flickering slowly. Toavoid this situation, the frame rate can be changed. The presentinvention has a capability to change frame rates. Also, it allows thevalue of N or M to be changed in N-fold pulse driving (a method whichpasses an N times larger current through EL elements 15 to illuminatethem for a period equal to 1/M of 1F).

The above capabilities are implemented byway of the switch 594. Theswitch 594 switches among the above capabilities when pressed more thanonce, following a menu on the screen 50.

Incidentally, the above items are not limited to cell phones. Needlessto say, they are applicable to television sets, monitors, etc. Also, itis preferable to provide icons on the display screen to allow the userto know at a glance what display mode he/she is in. The above itemssimilarly apply to the following.

The EL display apparatus and the like according to this embodiment canbe applied not only to video cameras, but also to digital cameras suchas the one shown in FIG. 60, still cameras, etc. The display apparatusis used as a screen 50 attached to a camera body 601. The camera body601 is equipped with a switch 594 as well as a shutter 603.

The display panel described above has a relatively small display area.However, with a display area of 30 inches or larger, the display screen50 tends to flex. To deal with this situation, the present inventionputs the display panel in a frame 611 and attaches a fitting 614 so thatthe frame 611 can be suspended as shown in FIG. 61. The display panel ismounted on a wall or the like using the fitting 614.

A large screen size increases the weight of the display panel. As ameasure against this situation, the display panel is mounted on a stand613, to which a plurality of legs 612 are attached to support the weightof the display panel.

The legs 612 can be moved from side to side as indicated by A. Also,they can be contracted as indicated by B. Thus, the display apparatuscan be installed even in a small space.

A television set in FIG. 61 has a surface of its screen covered with aprotective film (or a protective plate). One purpose of the protectivefilm is to prevent the surface of the display panel from breakage byprotecting from being hit by something. An AIR coat is formed on thesurface of the protective film. Also, the surface is embossed to reduceglare caused by extraneous light on the display panel.

A space is formed between the protective film and display panel byspraying beads or the like. Fine projections are formed on the rear faceof the protective film to maintain the space between the protective filmand display panel. The space prevents impacts from being transmittedfrom the protective film to the display panel.

Also, it is useful to inject an optical coupling agent into the spacebetween the protective film and display panel. The optical couplingagent may be a liquid such as alcohol or ethylene glycol, a gel such asacrylic resin, or a solid resin such as epoxy. The optical couplingagent can prevent interfacial reflection and function as a cushioningmaterial.

The protective film may be, for example, a polycarbonate film (plate),polypropylene film (plate), acrylic film (plate), polyester film(plate), PVA film (plate), etc. Besides, it goes without saying that anengineering resin film (ABS, etc.) may be used. Also, it may be made ofan inorganic material such as tempered glass. Instead of using aprotective film, the surface of the display panel may be coated withepoxy resin, phenolic resin, and acrylic resin 0.5 mm to 2.0 mm thick(both inclusive) to produce a similar effect. Also, it is useful toemboss surfaces of the resin.

It is also useful to coat surfaces of the protective film or coatingmaterial with fluorine. This will make it easy to wipe dirt from thesurfaces with a detergent. Also, the protective film may be made thickand used for a front light as well as for the screen surface.

The display panel according to the example of the present invention maybe used in combination with the three-side free configuration. Thethree-side free configuration is useful especially when pixels are builtusing amorphous silicon technology. Also, in the case of panels formedusing amorphous silicon technology, since it is difficult to controlvariations in the characteristics of transistor elements duringproduction processes, it is preferable to use the N-pulse driving, resetdriving, dummy pixel driving, or the like according to the presentinvention. That is, the transistors according to the present inventionare not limited to those produced by polysilicon technology, and theymay be produced by amorphous silicon technology.

Incidentally, the N-fold pulse driving (FIGS. 13, 16, 19, 20, 22, 24,30, etc.) and the like according to the present invention are moreeffective for display panels which contain transistors 11 formed bylow-temperature polysilicon technology than display panels which containtransistors 11 formed by amorphous silicon technology. This is becauseadjacent transistors, when formed by amorphous silicon technology, havealmost equal characteristics. Thus, driving currents for individualtransistors are close to a target value even if the transistors aredriven by current obtained by addition (the N-fold pulse driving inFIGS. 22, 24, and 30, in particular, are effective for pixelconfigurations containing amorphous silicon transistors).

The duty cycle control driving, reference current control, N-fold pulsedriving, and other drive methods and drive circuits according to thepresent invention described herein are not limited to drive methods anddrive circuits for organic EL display panels. Needless to say they arealso applicable to other displays such as field emission displays (FEDS)as shown in FIG. 221.

In an FED shown in FIG. 221, an electron emission protuberance 2213(which corresponds to the pixel electrode 105 in FIG. 10) which emitselectrons in a matrix is formed on a board 71. A pixel contains aholding circuit 2214 (which corresponds to the capacitor in FIG. 1)which holds image data received from a video signal circuit 2212 (whichcorresponds to the source driver circuit 14 in FIG. 1). Also, controlelectrodes 2211 are placed in front of the electron emissionprotuberance 2213. Voltage signals are applied to the control electrodes2211 by an on/off control circuit 2215 (which corresponds to the gatedriver circuit 12 in FIG. 1).

The pixel configuration in FIG. 221 can perform N-fold pulse driving,duty cycle control driving, etc. if a peripheral circuit shown in FIG.222 is added. An image data signal is applied to the source signal line18 from the video signal circuit 2212. A pixel 16 selection signal isapplied to a selection signal line 2221 by an on/off control circuit2215 a, and consequently pixels 16 are selected one after another andimage data is written into them. Also, an on/off signal is applied to anon/off signal line 2222 by an on/off control circuit 2215 b, andconsequently the FED of pixels is subjected to on/off control (dutycycle control).

The technical idea described in the example of the present invention canbe applied to video cameras, projectors, 3D television sets, projectiontelevision sets, etc. It can also be applied to viewfinders, cell phonemonitors, PHS, personal digital assistants and their monitors, anddigital cameras and their monitors.

Also, the technical idea is applicable to electrophotographic systems,head-mounted displays, direct view monitors, notebook personalcomputers, video cameras, electronic still cameras. Also, it isapplicable to ATM monitors, publicphones, videophones, personalcomputers, and wristwatches and its displays.

Furthermore, it goes without saying that the technical idea can beapplied to display monitors of household appliances, pocket gamemachines and their monitors, backlights for display panels, orilluminating devices for home or commercial use. Preferably,illuminating devices are configured such that color temperature can bevaried. Color temperature can be changed by forming RGB pixels instripes or in dot matrix and adjusting currents passed through them.Also, the technical idea can be applied to display apparatus foradvertisements or posters, RGB traffic lights, alarm lights, etc.

Also, organic EL display panels are useful as light sources forscanners. An image is read with light directed to an object using an RGBdot matrix as a light source. Needless to say, the light may bemonochromatic. Besides, the matrix is not limited to an active matrixand may be a simple matrix. The use of adjustable color temperature willimprove imaging accuracy.

Also, organic EL display panels are useful as backlights of liquidcrystal display panels. Color temperature can be changed and brightnesscan be adjusted easily by forming RGB pixels of an EL display panel(backlight) in stripes or in dot matrix and adjusting currents passedthrough them. Besides, the organic EL display panel, which provides asurface light source, makes it easy to generate Gaussian distributionthat makes the center of the screen brighter and perimeter of the screendarker. Also, organic EL display panels are useful as backlights offield-sequential liquid crystal display panels which scan with R, G, andB lights in turns. Also, they can be used as backlights of liquidcrystal display panels for movie display by inserting black even if thebacklights are turned on and off.

INDUSTRIAL APPLICABILITY

The source driver circuit of the present invention, in which transistorscomposing a current mirror are formed adjacent to each other, can reducevariations in output current caused by deviations in thresholds. Thus,it can reduce brightness irregularities of an EL display panel and hasgreat practical effect.

Also, the display panels, display apparatus, etc. of the presentinvention offer distinctive effects, including high quality, high moviedisplay performance, low power consumption, low costs, high brightness,etc., according to their respective configurations.

Incidentally, the present invention does not consume much power becauseit can provide power-saving information display apparatus. Also, it doesnot waste resources because it can reduce size and weight. Furthermore,it can adequately support high-resolution display panels. Thus, thepresent invention is friendly to both global environmental and spaceenvironment.

1. A driver circuit for an EL display panel comprising: referencecurrent generating means of generating a reference current; a firstcurrent source which is fed the reference current from the referencecurrent generating means and outputs a first current which correspondsto the reference current to a plurality of second current sources; thesecond current sources which are fed the first current outputted fromthe first current source and output a second current which correspondsto the first current to a plurality of third current sources; and thethird current sources which are fed the second current outputted fromthe second current sources and output a third current which correspondsto the second current to a plurality of fourth current sources,characterize in that among the fourth current sources, an appropriatenumber of unit current sources are selected according to input imagedata.
 2. A driver circuit for an EL display panel comprising: aplurality of current generator circuits each of which includes unittransistors equal in number to a power of two; switch circuits connectedto the respective current generator circuits; internal wiring connectedto output terminals; and a control circuit configured to turn on and offthe switch circuits according to input data, wherein a first end of eachswitch circuit is connected to the current generator circuit and asecond end of each switch circuit is connected to the internal wiring.3. The driver circuit for an EL display panel according to claim 2,wherein: channel width W of the unit transistors is from 2 to 9 μm bothinclusive, and size (WL) of the transistors is 4 square μm or more. 4.The driver circuit for an EL display panel according to claim 2,wherein: a ratio of channel length L to channel width W of the unittransistors is two or larger; and power supply voltage used is between2.5 V and 9 V both inclusive.
 5. A driver circuit for an EL displaypanel comprising: a first output current circuit including a pluralityof unit transistors configured to pass a first unit current; a secondoutput current circuit including a plurality of unit transistorsconfigured to pass a second unit current; and an output stage configuredto produce an output by adding an output current of the first outputcurrent circuit and an output current of the second output currentcircuit, wherein the first unit current is smaller than the second unitcurrent, the first output current circuit operates in a low gradationregion and a high gradation region according to gradations, and thesecond output current circuit operates in the high gradation regionaccording to gradations, and output current values of the first outputcurrent circuit do not change in the high gradation region when thesecond output current circuit operates.
 6. A driver circuit for an ELdisplay panel comprising: a programming current generator circuitincluding a plurality of unit transistors corresponding to outputterminals; first transistors configured to generate a first referencecurrent that defines a current flowing through the unit transistors;gate wiring connected to gate terminals of the plurality of firsttransistors; and second and third transistors whose gate terminals areconnected to the gate wiring and that form current mirror circuits inconjunction with the first transistors, wherein a second referencecurrent is supplied to the second and third transistors.
 7. The drivercircuit for an EL display panel according to claim 6, furthercomprising: a programming current generator circuit including aplurality of unit transistors corresponding to output terminals; aplurality of first transistors configured to form current mirrorcircuits in conjunction with the unit transistors; and a secondtransistor configured to generate a reference current flowing throughthe first transistors, wherein the reference current generated by thesecond transistor branches through the plurality of first transistors.8. The driver circuit for an EL display panel according to claim 6,wherein in a driver IC chip which includes the driver circuit, the thirdtransistor is electrically connected, in an area in which the firstreference current supply wirings are placed, to two outermost placedwirings of the reference current supply wiring group placed in the area.9. The driver circuit for an EL display panel according to claim 7,wherein in a driver IC chip which includes the driver circuit, the thirdtransistor is electrically connected, in an area in which the firstreference current supply wirings are placed, to two outermost placedwirings of the reference current supply wiring group placed in the area.10. An EL display apparatus comprising: a first substrate on whichdriver transistors are placed in a matrix and that contains a displayarea including EL elements formed corresponding to the drivertransistors; a source driver IC configured to apply a programmingcurrent or voltage to the driver transistors; a first wiring formed onthe first substrate located under the source driver IC; a second wiringelectrically connected to the first wiring and formed between the sourcedriver IC and the display area; and an anode wiring that branches fromthe second wiring and applies an anode voltage to pixels in the displayarea.
 11. The EL display apparatus according to claim 10, wherein thefirst wiring has a light shielding function.
 12. An EL display apparatuscomprising: a display area in which pixels with EL elements are formedin a matrix; driver transistors configured to supply light-emittingcurrent to the EL elements; and a source driver circuit configured tosupply programming current to the driver transistors, wherein the drivertransistors are P-channel transistors, and transistors that generate theprogramming current in the source driver circuit are N-channeltransistors.
 13. An EL display apparatus comprising: a display area inwhich EL elements, driver transistors configured to supplylight-emitting current to the EL elements, first switching elementsconfigured to form paths between the driver transistors and the ELelements, and second switching elements configured to form paths betweenthe driver transistors and source signal lines are formed in a matrix; afirst gate driver circuit configured to perform on/off control of thefirst switching elements; a second gate driver circuit configured toperform on/off control of the second switching elements; and a sourcedriver circuit configured to supply programming current to the drivertransistors, wherein the driver transistors are P-channel transistors,and transistors that generate the programming current in the sourcedriver circuit are N-channel transistors.
 14. An EL display apparatuscomprising: EL elements; P-channel driver transistors configured tosupply light-emitting current to the EL elements; switching transistorsformed between the EL elements and the driver transistors; a sourcedriver circuit configured to supply programming current; and gate drivercircuits configured to keep the switching transistors off for twohorizontal scanning periods or longer in one frame period.